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PK60N512VMD100 Datasheet(PDF) 69 Page - Freescale Semiconductor, Inc |
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PK60N512VMD100 Datasheet(HTML) 69 Page - Freescale Semiconductor, Inc |
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69 / 80 page  Table 50. I2S/SAI master mode timing in Normal Run, Wait and Stop modes (full voltage range) (continued) Num. Characteristic Min. Max. Unit S7 I2S_TX_BCLK to I2S_TXD valid — 15 ns S8 I2S_TX_BCLK to I2S_TXD invalid 0 — ns S9 I2S_RXD/I2S_RX_FS input setup before I2S_RX_BCLK 20.5 — ns S10 I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0 — ns S1 S2 S2 S3 S4 S4 S5 S9 S7 S9 S10 S7 S8 S6 S10 S8 I2S_MCLK (output) I2S_TX_BCLK/ I2S_RX_BCLK (output) I2S_TX_FS/ I2S_RX_FS (output) I2S_TX_FS/ I2S_RX_FS (input) I2S_TXD I2S_RXD Figure 30. I2S/SAI timing — master modes Table 51. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (full voltage range) Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.6 V S11 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 80 — ns S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low (input) 45% 55% MCLK period S13 I2S_TX_FS/I2S_RX_FS input setup before I2S_TX_BCLK/I2S_RX_BCLK 5.8 — ns S14 I2S_TX_FS/I2S_RX_FS input hold after I2S_TX_BCLK/I2S_RX_BCLK 2 — ns S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid • Multiple SAI Synchronous mode • All other modes — — 24 20.6 ns S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0 — ns Table continues on the next page... Peripheral operating requirements and behaviors K60 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 69 |
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