AD73311ARSZ datasheet(19/36 Pages) AD

Part #	AD73311ARSZ

Description	Low Cost, Low Power CMOS General Purpose Analog Front End

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AD73311

–19–

REV. B

Program (Control) Mode

In Program Mode, CRA:0 = 0, the user writes to the control

registers to set up the device for desired operation—SPORT

operation, cascade length, power management, input/output

gain, etc. In this mode, the 16-bit information packet sent to the

device by the DSP engine is interpreted as a control word whose

format is shown in Table X. In this mode, the user must address

the device to be programmed using the address field of the

control word. This field is read by the device and if it is zero

(000 bin) then the device recognizes the word as being addressed

to it. If the address field is not zero, it is then decremented and

the control word is passed out of the device—either to the next

device in a cascade or back to the DSP engine. This 3-bit

address format allows the user to uniquely address any one of

up to eight devices in a cascade; please note that this addressing

scheme is valid only in sending control information to the device

—a different format is used to send DAC data to the device(s).

In a single codec configuration, all control word addresses must

be zero, otherwise they will not be recognized; in a multi-codec

configuration all addresses from zero to N-1 (where N = number

of devices in cascade) are valid.

Following reset, when the SE pin is enabled, the codec responds

by raising the SDOFS pin to indicate that an output sample

event has occurred. Control words can be written to the device

to coincide with the data being sent out of the SPORT, as

shown in Figure 10, or they can lag the output words by a time

interval that should not exceed the sample interval. After reset,

output frame sync pulses will occur at a slower default sample

rate, which is DMCLK/2048, until Control Register B is program-

med after which the SDOFS pulses will revert to the DMCLK/256

rate. This is to allow slow controller devices to establish com-

munication with the AD73311. During Program Mode, the

data output by the device is random and should not be inter-

preted as ADC data.

Data Mode

Once the device has been configured by programming the cor-

rect settings to the various control registers, the device may exit

Program Mode and enter Data Mode. This is done by program-

ming the DATA/

PGM (CRA:0) bit to a 1 and MM (CRA:1) to

0. Once the device is in Data Mode, the 16-bit input data frame

is now interpreted as DAC data rather than a control frame.

This data is therefore loaded directly to the DAC register. In

Data Mode, as the entire input data frame contains DAC data,

the device relies on counting the number of input frame syncs

received at the SDIFS pin. When that number equals the device

count stored in the device count field of CRA, the device knows

that the present data frame being received is its own DAC up-

date data. When the device is in normal Data Mode (i.e., mixed

mode disabled), it must receive a hardware reset to reprogram

any of the control register settings. In a single codec configura-

tion, each 16-bit data frame sent from the DSP to the device is

interpreted as DAC data. The default device count is 1, therefore

each input frame sync will cause the 16-bit data frame to be

loaded to the DAC register.

Appendix A details the initialization and operation of a single

codec in normal Data Mode, while Appendix C details the

initialization and operation of a dual codec cascade in normal

Data Mode.

Mixed Program/Data Mode

This mode allows the user to send control words to the device

along with the DAC data. This permits adaptive control of the

device whereby control of the input/output gains can be effected

by interleaving control words along with the normal flow of

DAC data. The standard data frame remains 16 bits, but now

the MSB is used as a flag bit to indicate whether the remaining

15 bits of the frame represent DAC data or control information.

In the case of DAC data, the 15 bits are loaded with MSB justi-

fication and LSB set to 0 to the DAC register. Mixed mode is

enabled by setting the MM bit (CRA:1) to 1 and the DATA/

PGM bit (CRA:0) to 1. In the case where control setting

changes will be required during normal operation, this mode

allows the ability to load both control and data information with

the slight inconvenience of formatting the data. Note that the

output samples from the ADC will also have the MSB set to

zero to indicate it is a data word.

A description of a single device operating in mixed mode is

detailed in Appendix B, while Appendix D details the initializa-

tion and operation of a dual codec cascade operating in mixed

mode. Note that it is not essential to load the control registers in

Program Mode before setting mixed mode active. It is also

possible to initiate mixed mode by programming CRA with the

first control word and then interleaving control words with

DAC data.

Analog Loop-Back

This mode can be used for diagnostic purposes and allows the

user to feed the ADC samples from the ADC register directly to

the DAC register. This forms a loop-back of the analog input to

the analog output by reconstructing the encoded signal using

the decoder channel. The serial interface will continue to work,

which allows the user to control gain settings, etc. Only when

ALB is enabled with mixed mode operation can the user disable

the ALB, otherwise the device must be reset.

Digital Loop-Back

This mode allows the user to verify the DSP interfacing and

connection by writing words to the SPORT of the devices and

have them returned back unchanged after a delay of 16 SCLK

cycles. The frame sync and data word that are sent to the device

are returned via the output port. Again, DLB mode can only be

disabled when used in conjunction with mixed mode, otherwise

the device must be reset.

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