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TLP118 Datasheet(PDF) 4 Page - Toshiba Semiconductor |
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TLP118 Datasheet(HTML) 4 Page - Toshiba Semiconductor |
4 / 13 page TLP118 2010-03-02 4 Switching Characteristics (Unless otherwise specified, Ta=-40 to 125 °C、VCC=4.5 to 5.5V) CHARACTERISTIC SYMBOL TEST CIRCUIT CONDITION MIN TYP. MAX UNIT Propagation delay time (H→L) tpHL IF=0→7.5 mA - 30 60 ns Propagation delay time (L→H) tpLH IF=7.5→0 mA RL=350Ω CL=15pF (Note 4) - 30 60 ns Switching Time Dispersion between ON and OFF |tpHL- tpLH| - - 30 ns Propagation Delay Skew (Note 5) tpsk IF=0↔7.5 mA RL=350Ω, CL=15pF (Note 4) -40 - 40 ns Fall Time (90 – 10 %) tf IF=0→7.5 mA - 30 - ns Rise Time (10 – 90 %) tr 5 IF=7.5→0 mA RL=350Ω CL=15pF (Note 4) - 30 - ns Common Mode transient Immunity at High Level Output CMH VCM=1000 Vp-p , IF=0 mA, VCC=5 V , Ta=25°C 15 - - kV/μs Common Mode transient Immunity at Low Level Output CML 6 VCM=1000 Vp-p , IF=10 mA, VCC=5 V , Ta=25 °C -15 - - kV/μs *All typical values are at Ta=25 °C Note 3: A ceramic capacitor (0.1 μF) should be connected from pin 6 (VCC) to pin 4 (GND) to stabilize the operation of the high gain linear amplifier. Failure to provide the bypass may impair the switching property. The total lead length between capacitor and coupler should not exceed 1 cm. Note 4: f=5MHz, duty=50%, input current tr=tf=5ns, CL is approximately 15pF which includes probe and Jig/stray wiring capacitance. Note 5: Propagation delay skew is defined as the difference between the largest and smallest propagation delay times (i.e. tpHL or tpLH) of multiple samples. Evaluations of these samples are conducted under identical test conditions (supply voltage, input current, temperature, etc). TEST CIRCUIT 1: IOH Test Circuit TEST CIRCUIT 2: VOL Test Circuit TEST CIRCUIT 3: ICCL Test Circuit TEST CIRCUIT 4: ICCH Test Circuit IF A VCC 0.1 μF ICCL 0.1μF VOL VCC V IO ↑ SHIELD IF SHIELD A VCC 0.1 μF ICCH SHIELD 0.1μF SHIELD VF VCC IOH A VO |
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