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AD8170AN Datasheet(PDF) 10 Page - Analog Devices |
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AD8170AN Datasheet(HTML) 10 Page - Analog Devices |
10 / 16 page AD8170/AD8174 –10– REV. 0 20ns/DIV OUTPUT VOUT = ±1V INPUT VIN = ±0.5V VOUT = 2V p-p G = +2 RF = 499 (AD8170R) RF = 549 (AD8174R) CL = 300PF RS(OUT) = 15 Figure 25. Pulse Response Driving a Large Load Capacitor, CL = 300 pF Overload Behavior and Recovery There are three important overload conditions: input voltage overdrive, output voltage overdrive and current overload at the amplifier’s negative feedback input. At a gain of 1, recovery from driving the input voltages beyond the voltage range of the input switches is very quick, typically less than 30 ns. Recovery from output overdrive is somewhat slower and depends on how much the output is overdriven. Recovery from 15% overdrive is under 60 ns. 50% overdrive produces recovery times of about 85 ns. Input overdrive in a high gain application can result in a large current flow in the input stage. This current is internally limited to 40 mA. The effect on total power dissipation should be taken into account. LAYOUT CONSIDERATIONS: Realizing the high speed performance attainable with the AD8170 and AD8174 requires careful attention to board layout and component selection. Proper RF design techniques and low parasitic component selection are mandatory. Wire wrap boards, prototype boards, and sockets are not recommended because of their high parasitic inductance and capacitance. Instead, surface-mount components should be soldered directly to a printed circuit board (PCB). The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low impedance ground path. The ground plane should be removed from the area near input and output pins to reduce stray capacitance. Chip capacitors should be used for supply bypassing. One end of the capacitor should be connected to the ground plane and the other within 1/4 inch of each power pin. An additional large (4.7 µF–10 µF) tantalum capacitor should be connected in parallel with each of the smaller capacitors for low impedance supply bypassing over a broad range of frequencies. Signal traces should be as short as possible. Stripline or microstrip techniques should be used for long signal traces (longer than about 1 inch). These should be designed with a characteristic impedance of 50 Ω or 75 Ω and be properly terminated at each end using surface mount components. Careful layout is imperative to minimize crosstalk. Guards (ground or supply traces) must be run between all signal traces to limit direct capacitive coupling. Input and output signal lines should fan out away from the mux as much as possible. If multiple signal layers are available, a buried stripline structure having ground plane above, below, and between signal traces will have the best crosstalk performance. Return currents flowing through termination resistors can also increase crosstalk if these currents flow in sections of the finite- impedance ground circuit that is shared between more than one input or output. Minimizing the inductance and resistance of the ground plane can reduce this effect, but further care should be taken in positioning the terminations. Terminating cables directly at the connectors will minimize the return current flowing on the board, but the signal trace between the connector and the mux will look like an open stub and will degrade the frequency response. Moving the termination resistors close to the input pins will improve the frequency response, but the terminations from neighboring inputs should not have a common ground return. APPLICATIONS 8-to-1 Video Multiplexer Two AD8174 4-to-1 multiplexers can be combined with a single digital inverter to yield an 8-to-1 multiplexer as shown in Figure 26. The ENABLE control pin allows the two op amp outputs to be connected together directly. Taking the ENABLE pin high shuts off the supply current to the output op amp and places the op amp’s output and inverting input (Pin 12, –VIN) in high impedance states. The two least significant bits (LSBs) of the address lines connect directly to the A0 and A1 inputs of both AD8174 devices. The third address line connects directly to the ENABLE input on one device and is inverted before being applied to the ENABLE input on the second device. As a result, when one device is enabled, the second device presents a high impedance. The op amp of the enabled device must however drive both feedback networks ((549 Ω + 549 Ω)/2). The gain of this multiplexer has been set to +2 in this example. This gives an overall gain of +1 when back terminated lines are used. In applications where switching and settling times are critical, the digital control pins (A0, A1 and ENABLE) should also be appropriately terminated (with either 50 Ω or 75 Ω). |
Similar Part No. - AD8170AN |
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Similar Description - AD8170AN |
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