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AD7740KRMZ Datasheet(PDF) 2 Page - Analog Devices

Part No. AD7740KRMZ
Description  3 V/5 V Low Power, Synchronous Voltage-to-Frequency Converter
Download  11 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

AD7740KRMZ Datasheet(HTML) 2 Page - Analog Devices

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AD7740 SPECIFICATIONS
K, Y Versions
1
Parameter
2
Min
Typ
Max
Unit
Test Conditions/Comments
DC PERFORMANCE
Integral Nonlinearity
CLKIN = 32 kHz
3
±0.012
% of Span
4
Unbuffered Mode, External Clock at CLKIN
CLKIN = 1 MHz
±0.012
% of Span
Unbuffered Mode, Crystal at CLKIN
CLKIN = 32 kHz
3
±0.018
% of Span
Buffered Mode, External Clock at CLKIN
CLKIN = 1 MHz
±0.018
% of Span
Buffered Mode, Crystal at CLKIN
Offset Error
±7
±35
mV
Unbuffered Mode, VIN = 0 V
±7
±35
mV
Buffered Mode, VIN = 0.1 V
Gain Error
±0.1
±0.7
% of Span
Offset Error Drift
3
±20
µV/°C
Gain Error Drift
3
±4
ppm of Span/
°C
Power Supply Rejection Ratio
3
–55
dB
∆VDD = ±5% (5 V)
–65
dB
∆VDD = ±10% (3.3 V)
ANALOG INPUT, VIN
Nominal Input Span
0 – VREF
V
±150 mV Overrange Available
0.1
VDD – 0.2
V
Buffered Mode
Input Current
8
10
µA
Unbuffered Mode, VIN = 5.4 V, REFIN = 5.25 V
5
100
nA
Buffered Mode, VIN = 0.1 V, REFIN = 2.5 V
REFERENCE VOLTAGE
REFIN
5
Nominal Input Voltage
2.5
VDD
V
REFOUT
Output Voltage
2.3
2.5
2.7
V
Output Impedance
3
1k
See Pin Function Description
Reference Drift
3
±50
ppm/
°C
Line Rejection
3
–75
dB
∆VDD = ±5% (5 V)
Line Rejection
3
–60
dB
∆VDD = ±10% (3.3 V)
Reference Noise (0.1 Hz to 10 Hz)
3
100
µV p–p
FOUT OUTPUT
Nominal Frequency Span
0.1 fCLKIN to 0.9 fCLKIN
Hz
VIN = 0 V to VREF. See Figure 2
LOGIC INPUTS (CLKIN, BUF)
3
CLKIN
Input Frequency
32
1000
kHz
For Specified Performance
Input High Voltage, VIH
3.5
V
VDD = 5 V
± 5%
Input High Voltage, VIH
2.5
V
VDD = 3.3 V
± 10%
Input Low Voltage, VIL
0.8
V
VDD = 5 V
± 5%
Input Low Voltage, VIL
0.4
V
VDD = 3.3 V
± 10%
Input Current
±2
µA
VIN = 0 V to VDD
Pin Capacitance
3
10
pF
BUF
Input High Voltage, VIH
2.4
V
VDD = 5 V
± 5%
Input High Voltage, VIH
2.1
V
VDD = 3.3 V
± 10%
Input Low Voltage, VIL
0.8
V
VDD = 5 V
± 5%
Input Low Voltage, VIL
0.4
V
VDD = 3.3 V
± 10%
Input Current
±100
nA
Pin Capacitance
3
10
pF
LOGIC OUTPUTS (FOUT, CLKOUT)
3
Output High Voltage, VOH
4.0
V
Output Sourcing 200
µA6. VDD = 5 V ± 5%
Output High Voltage, VOH
2.1
V
Output Sourcing 200
µA6. VDD = 3.3 V ± 10%
Output Low Voltage, VOL
0.1
0.4
V
Output Sinking 1.6 mA
6
POWER REQUIREMENTS
VDD
7
3.0
5.25
V
IDD (Normal Mode)
8
0.9
1.25
mA
VIH = VDD, VIL= GND. Unbuffered Mode
IDD (Normal Mode)
8
1.1
1.5
mA
VIH = VDD, VIL= GND. Buffered Mode
IDD (Power-Down)
30
100
µA
Power-Up Time
3
30
µs
Exiting Power-Down (Ext. Clock at CLKIN)
NOTES
1Temperature range: K Version, 0
°C to +85°C; Y Version, –40°C to +105°C; typical specifications are at 25°C.
2See Terminology.
3Guaranteed by design and characterization, not production tested.
4Span = Max output frequency–Min output frequency.
5Because this pin is bidirectional, any external reference must be capable of sinking/sourcing 400
µA in order to overdrive the internal reference.
6These logic levels apply to CLKOUT only when it is loaded with one CMOS load.
7Operation at VDD = 2.7 V is also possible with degraded specifications.
8Outputs unloaded. I
DD increases by CL
× V
OUT
× f
FOUT when FOUT is loaded. If using a crystal/resonator as the clock source, IDD will vary depending on the crystal/resonator
type (see Clock Generation section).
Specifications subject to change without notice.
REV. A
–2–
(VDD = 3.0 V to 3.6 V, 4.75 V to 5.25 V, GND = 0 V, REFIN = 2.5 V; CLKIN = 1 MHz; All
specifications TMIN to TMAX unless otherwise noted.)


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