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AD7304BR-REEL Datasheet(PDF) 9 Page - Analog Devices

Part No. AD7304BR-REEL
Description  3 V/5 V, Rail-to-Rail Quad, 8-Bit DAC
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD7304BR-REEL Datasheet(HTML) 9 Page - Analog Devices

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AD7304/AD7305
Rev. C | Page 9 of 20
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VOUTA
VSS
VREF
DB7
LDAC
GND
VOUTB
VOUTD
VDD
A0/SHDN
DB0
WR
A1
DB4
DB5
DB6
DB3
DB2
DB1
VOUTC
AD7305
TOP VIEW
(Not to Scale)
Figure 9. AD7305 Pin Configuration
Table 8. AD7305 Pin Function Description
Pin No.
Mnemonic
Description
1
VOUTB
Channel B Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to VREFB pin. Output is
open circuit when SHDN is enabled.
2
VOUTA
Channel A Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to VREFA pin. Output is
open circuit when SHDN is enabled.
3
VSS
Negative Power Supply Input. Specified range of operation is 0 V to –5.5 V.
4
VREF
Channel B Reference Input. Establishes VOUT full-scale voltage. Specified range of operation is VSS < VREF < VDD.
5
GND
Common Analog and Digital Ground.
6
LDAC
Load DAC Register Strobe, Active Low. Simultaneously transfers data from all four input registers into the
corresponding DAC registers. Asynchronous active low input. DAC register is transparent when LDAC = 0. See Table 6
for operation.
7
DB7
MSB Digital Input Data Bit.
8
DB6
Data Bit 6.
9
DB5
Data Bit 5.
10
DB4
Data Bit 4.
11
DB3
Data Bit 3.
12
DB2
Data Bit 2.
13
DB1
Data Bit 1.
14
DB0
LSB Digital Input Data Bit.
15
WR
Write Data into Input Register Control Line, Active Low. See Table 6 for operation.
16
A1
Address Bit 1.
17
A0/SHDN
Address Bit 0/Hardware Shutdown (SHDN) Control Input, Active When Pin Is Left Floating by a Three-State Logic
Driver. Does not effect DAC register contents as long as power is present on VDD.
18
VDD
Positive Power Supply Input. Specified range of operation is 2.7 V to 5.5 V.
19
VOUTD
Channel D Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to VREFD pin. Output is
open circuit when SHDN is enabled.
20
VOUTC
Channel C Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to VREFC pin. Output is
open circuit when SHDN is enabled.


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