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AD7304BR-REEL Datasheet(PDF) 7 Page - Analog Devices |
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AD7304BR-REEL Datasheet(HTML) 7 Page - Analog Devices |
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7 / 20 page 
AD7304/AD7305 Rev. C | Page 7 of 20 Table 6. AD7305 Control Logic Truth Table WR 1 A1 A0 LDAC2 Input Register Function DAC Register Function L L L H Register A loaded with DB0 to DB7 Latched with previous contents, no change ↑+ L L H Register A latched with DB0 to DB7 Latched with previous contents, no change L L H H Register B loaded with DB0 to DB7 Latched with previous contents, no change ↑+ L H H Register B latched with DB0 to DB7 Latched with previous contents, no change L H L H Register C loaded with DB0 to DB7 Latched with previous contents, no change ↑+ H L H Register C latched with DB0 to DB7 Latched with previous contents, no change L H H H Register D loaded with DB0 to DB7 Latched with previous contents, no change ↑+ H H H Register D latched with DB0 to DB7 Latched with previous contents, no change H X X L No effect All input register contents loaded, register transparent L X X L Input register x transparent to DB0 to DB7 Register transparent H X X ↑+ No effect All input register contents latched H X X H No effect, device not selected No effect, device not selected 1 ↑+ positive logic transition; ↓– negative logic transition; X don’t care. 2 LDAC is a level-sensitive input. tAH tDH tLH tLDW tWR tAS tDS tLS tS ±1 LSB ERROR BAND A0, A1 WR D0–D7 LDAC VOUT Figure 6. AD7305 General Timing Diagram tSDR A0/SHDN IDD tSDN Figure 7. AD7305 Timing Diagram Zoom In |
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