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TLV5610IPWR Datasheet(PDF) 11 Page - Texas Instruments

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Part No. TLV5610IPWR
Description  8-CHANNEL, 12-/10-/8-BIT, 2.7-V TO 5.5-V LOW POWER
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TLV5610IPWR Datasheet(HTML) 11 Page - Texas Instruments

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APPLICATION INFORMATION
GENERAL FUNCTION
REF
CODE
0x1000
[V]
(1)
POWER ON RESET (POR)
SERIAL INTERFACE
SCLK
FS
DIN
SCLK
FS
F15
F15
X
X
E0
X
E1
E14
E15
D0
D1
D14
D15
X
DIN
F15
F15
X
X
E1
E0
E14
E15
X
D0
D1
D14
D15
X
DSP Mode:
µC Mode:
TLV5608
TLV5610
TLV5629
www.ti.com.................................................................................................................................................... SLAS268G – MAY 2000 – REVISED NOVEMBER 2008
The TLV5610, TLV5608, and TLV5629 are 8-channel, 12-bit, single-supply DACs, based on a resistor string
architecture. They consist of a serial interface, a speed and power-down control logic, a reference input buffer, a
resistor string, and a rail-to-rail output buffer.
The output voltage (full scale determined by external reference) for each channel is given by:
where REF is the reference voltage and CODE is the digital input value. The input range is 0x000 to 0xFFF for
the TLV5610, 0x000 to 0xFFC for the TLV5608, and 0x000 to 0xFF0 for the TLV5629.
The built-in power-on-reset circuit controls the output voltage after power up. On power up, all latches including
the preset register are set to zero, but the DAC outputs are only set to zero if the LDAC is low. The DAC outputs
may have a small offset error produced by the output buffer. The registers remains at zero until a valid write
sequence is made to the DAC, changing the DAC register data. This is useful in applications where it is
important to know the state of the outputs of the DAC after power up. All digital inputs must be logic low until the
digital and analog supplies are applied. Any logic high voltages applied to the logic input pins when power is not
applied to AVDD and DVDD, may power the device logic circuit through the overvoltage protection diode causing
an undesired operation. When separate analog (AVDD) and digital (DVDD) supplies are used, AVDD must come up
first before DVDD, to ensure that the power-on-reset circuit operates correctly.
A falling edge of FS starts shifting the data on DIN starting with the MSB to the internal register on the falling
edges of SCLK. After 16 bits have been transferred, the content of the shift register is moved to one of the DAC
holding registers, depending on the address bits within the data word. A logic 0 on the LDAC pin is required to
transfer the content of the DAC holding register to the DAC latch and to update the DAC outputs. LDAC is an
asynchronous input. It can be held low if a simultaneous update of all eight channels is not needed.
For daisy-chaining, DOUT provides the data sampled on DIN with a delay of 16 clock cycles.
Figure 13. Data Sampled on DIN
Copyright © 2000–2008, Texas Instruments Incorporated
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Product Folder Link(s): TLV5608 TLV5610 TLV5629


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