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TMS370C340ANJT Datasheet(PDF) 11 Page - Texas Instruments |
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TMS370C340ANJT Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 69 page  TMS370Cx4x 8-BIT MICROCONTROLLER SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997 11 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443 program EPROM The TMS370C742A device contains 8K bytes of EPROM mapped, beginning at location 6000h and continuing through location 7FFFh. Memory addresses 7FE0h through 7FEBh are reserved for Texas Instruments (TI), and memory addresses 7FECh through 7FFFh are reserved for interrupt and reset vectors. Trap vectors, used with TRAP0 through TRAP15 instructions, are located between addresses 7FC0h and 7FDFh. Reading the program EPROM modules is identical to reading other internal memory. During programming, the EPROM is controlled by the EPROM control register (EPCTL). The program EPROM module features include: D Programming -- In-circuit programming capability if VPP is applied to MC -- Control register: EPROM programming is controlled by the EPROM control register (EPCTL) located in the peripheral file (PF) frame at location P01C as shown in Table 5. D Write protection: writes to the program EPROM are disabled under the following conditions: -- Reset: All programming to the EPROM module is halted. -- Low-power modes -- 13 V not applied to MC program ROM The program ROM consists of 4K or 8K bytes of mask-programmable read-only memory. The program ROM is used for permanent storage of data or instructions. Memory addresses 7FE0h through 7FEBh are reserved for TI, and memory addresses 7FECh through 7FFFh are reserved for interrupt and reset vectors. Trap vectors, used with TRAP0 through TRAP15 instructions, are located between addresses 7FC0h and 7FDFh. Programming of the mask ROM is performed at the time of device fabrication. system reset The system-reset operation ensures an orderly start-up sequence for the TMS370Cx4x CPU-based device. There are up to three different actions that can cause a system reset to the device. Two of these actions are generated internally, while one (RESET pin) is controlled externally. These actions are as follows: D Watchdog (WD) timer. A watchdog-generated reset occurs if an improper value is written to the WD key register, or if the re-initialization does not occur before the watchdog timer timeout . See the TMS370 Family User’s Guide (literature number SPNU127) for more information. D Oscillator reset. Reset occurs when the oscillator operates outside of the recommended operating range. See the TMS370 Family User’s Guide (literature number SPNU127) for more information. D External RESET pin. A low level signal can trigger an external reset. To ensure a reset, the external signal should be held low for one SYSCLK cycle. Signals of less than one SYSCLK can generate a reset. See the TMS370 Family User’s Guide (literature number SPNU127) for more information. Once a reset source is activated, the external RESET pin is driven (active) low for a minimum of eight SYSCLK cycles. This allows the ’x4x device to reset external system components. Additionally, if a cold start (VCC is off for several hundred milliseconds) condition or oscillator failure occurs or the RESET pin is held low, then the reset logic holds the device in a reset state for as long as these actions are active. After a reset, the program can check the oscillator-fault flag (OSC FLT FLAG, SCCR0.4), the cold-start flag (COLD START, SCCR0.7) and the watchdog reset (WD OVRFL INT FLAG, T1CTL2.5) to determine the source of the reset. A reset does not clear these flags. Table 6 lists the reset sources. TI is a trademark of Texas Instruments Incorporated. |
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