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NCP5269 Datasheet(PDF) 9 Page - ON Semiconductor

Part No. NCP5269
Description  Synchronous Buck Controller with Auto Power Controller with Auto Power Inputs for System Agent
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com

NCP5269 Datasheet(HTML) 9 Page - ON Semiconductor

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External Reference Voltage
NCP5269 accepts external reference voltage. To enable
this feature, tie V3 to VCC and feed V1 from external
reference. Then internal 650 mV reference is replaced by the
voltage on V1 pin. The output voltage is programmed by
resistor hooked from FB to FBRTN. VID0 and VID1 are
disabled with this function. Please ground both VID0 and
VID1 pins. All the resistors on Vref, V1, V2 and V3 are
removed. The soft−start cap CSS remains on the Vref pin.
The V2 pin can be left open.
The reference voltage on V1 pin can be from 0.5 V to
2.0 V. However, the NCP5269 does not provide
soft−transient feature, forced CCM operation and PG
blanking for any reference voltage jump on V1. Therefore,
external slewrate control or R/C is recommended to soften
the reference voltage change on V1 pin input. In addition,
minimum load current is required to discharge the output
voltage when the reference voltage on V1 pin moves lower,
in order to avoid false PG failure. For example, 1 mA
minimum load current is needed to discharge the output
voltage, given 0.5 mF output capacitance and external R =
10 k
W, C = 1 mF on the V1 pin to slow down the reference
voltage change. The minimum load current requirement is
proportional to the output capacitance and V1 pin reference
voltage slewrate. The initial reference voltage on V1 pin
should be established prior to EN assertion.
Differential Sensing of Output Voltage
The NCP5269 combines differential sensing with a high
accuracy VID DAC, referenced by a precision band gap
source and a low offset error amplifier, to provide accurate
output voltage. The output voltage is sensed between the FB
and FBRTN pins. FB should be connected through a resistor
to the positive regulation point. FBRTN should be connected
directly to the negative remote sensing point.
External Soft−Start and VID Change Slew Rate
To limit the start−up inrush current, a capacitor can be
connected from Vref pin to ground to ramp up reference
voltage slowly. During this period, the set amplifier output
mA current to charge capacitor CSS. The soft start period
can be calculated by the following equation:
tSS + −RA @ CSS @ LN 1 *
RA is the sum of the series resistors from VREF to
ground. RA = R3 + R4 + R5 + R6
ISA1 is soft start current 20 mA.
Vo is the initial output voltage set by VID
The output current of the set amplifier will change to
mA /− 90 mA after soft start period. So during voltage
steps due to VID bit change, the slew rate of output voltage
can be calculated as follows:
tSL + −RA @ CSS @ LN 1 *
VO2 * VO1
ISA2 is the source/sink current limit of set amplifier
during VID changing, which is 73/90
VO1 and VO2 are the voltages selected by VID inputs
Oscillator Frequency
A fixed precision oscillator is provided. The actual
switching frequency is set at 300 KHz, 400 KHz or 600 KHz
by the resistor on GL/FSET pin. The resistor and frequency
can be referred to the table below.
GL/FSET Resistor
Switching Frequency
300 KHz
400 KHz
600 KHz
Error Amplifier
The error amplifier’s primary function is to regulate the
converter’s output voltage, as shown in the Applications
Schematic. A type III compensation network must be
connected around the error amplifier to stabilize the
converter. It has a bandwidth of greater than 15 MHz, with
open loop gain of at least 80 dB. The COMP output voltage
is clamped to a level above the oscillator ramp in order to
improve large−scale transient response.
Soft Stop
Soft−Stop or discharge mode is always on during faults or
disable. In this mode, a fault (UVP, OVP, OCP, TSD) or
disable (EN) causes the output to be discharged through an
internal 20−ohm transistor inside of VO terminal. The time
constant of soft−stop is a function of output capacitance and
the resistance of the discharge transistor.
Adaptive Non−Overlap Gate Driver
In a synchronous buck converter, a certain dead time is
required between the low side drive signal and high side
drive signal to avoid shoot through. During the dead time,
the body diode of the low side FET free
-wheels the current.
The body diode has much higher voltage drop than that of
the MOSFET, which reduces the efficiency significantly.
The longer the body diode conducts, the lower the
efficiency. NCP5269 implements adaptive dead time
control to minimize the dead time, as well as preventing
shoot through from happening.
Automatic Power Saving Mode
If the load current decreases, the converter will enter
power save mode operation. During power save mode, the
converter skips switching and operates with reduced
, which minimizes the quiescent current and
maintains high efficiency.
Under Voltage Lockout (UVLO)
There is under
-voltage lock out protections (UVLO) for
VCC in NCP5269, which has a typical trip threshold voltage
4.2 V and trip hysteresis 300 mV. If UVLO is triggered, the
device resets and waits for the voltage to rise up over the

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