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ADSP-2191MKST-160 Datasheet(PDF) 32 Page - Analog Devices |
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ADSP-2191MKST-160 Datasheet(HTML) 32 Page - Analog Devices |
32 / 52 page ADSP-2191M –32– REV. 0 Host Port ACC Mode Read Cycle Timing Table 18 and Figure 17 describe Host port read operations in Address Cycle Control (ACC) mode. For more information on ACK, Ready, ALE, and ACC mode selection, see the Host port modes description on page 8. Table 18. Host Port ACC Mode Read Cycle Timing Parameter Min Max Unit Switching Characteristics tRHKS1 HRD Asserted to HACK Asserted (ACK Mode) First Byte 12tHCLK 15tHCLK+tNH 1 1t NH are peripheral bus latencies (n tHCLK); these are internal DSP latencies related to the number of peripherals attempting to access DSP memory at the same time. ns tRHKS2 HRD Asserted to HACK Asserted (Setup, ACK Mode)2 2Measurement is for the second, third, or fourth byte of a host read transaction. The quantity of bytes to complete a host read transaction is dependent on the data bus size (8 or 16 bits) and the data type (16 or 24 bits). 10 ns tRHKH HRD Deasserted to HACK Deasserted (Hold, ACK Mode) 10 ns tRHS HRD Asserted to HACK Asserted (Setup, Ready Mode) 10 ns tRHH HRD Asserted to HACK Deasserted (Hold, Ready Mode) First Byte 12tHCLK 15tHCLK+tNH 1 ns tRDH HRD Deasserted to Data Invalid (Hold) 1 ns tWSHKS HWR Asserted to HACK Asserted (Setup) During Address Latch 10 ns tWHHKH HWR Deasserted to HACK Deasserted (Hold) During Address Latch 10 ns tRDD HRD Deasserted to Data Disable 10 ns Timing Requirements tCSAL HCMS or HCIOMS Asserted to HALE Asserted (Delay) 0ns tALCS HALE Deasserted to Optional HCMS or HCIOMS Deasserted 1ns tRCSW HRD Deasserted to HCMS or HCIOMS Deasserted 0 ns tALW HALE Asserted to HWR Asserted 0.5 ns tALER HALE Deasserted to HWR Asserted 1 ns tCSR HCMS or HCIOMS Asserted to HRD Asserted 0ns tRCS HRD Deasserted (After Last Byte) to HCMS or HCIOMS Deasserted (Ready for Next Read) 0ns tWAL HWR Deasserted to HALE Deasserted (Delay) 2.5 ns tHKRD HACK Asserted to HRD Deasserted (Hold, ACK Mode) 1.5 ns tADW Address Valid to HWR Deasserted (Setup) 2 ns tWAD HWR Deasserted to Address Invalid (Hold) 1 ns tHKWAL HACK Asserted to HWR Deasserted (Hold) During Address Latch2 2ns |
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