TLV5626IDG4 datasheet(10/19 Pages) TI | 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN

Part No.	TLV5626IDG4

Description	2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN

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TLV5626

2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG

CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN

SLAS236A –JUNE 1999 – REVISED JUNE 2000

10

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 12

–1.0

–0.8

–0.6

–0.4

–0.2

–0.0

0.2

0.4

0.6

0.8

1.0

0

16

32

48

64

80

96

112

128

144

160

176

192

208

224

240

256

Digital Output Code

INTEGRAL NONLINEARITY

vs

DIGITAL OUTPUT CODE

APPLICATION INFORMATION

general function

The TLV5626 is a dual 8-bit, single supply DAC, based on a resistor string architecture. It consists of a serial

interface, a speed and power-down control logic, a programmable internal reference, a resistor string, and a

rail-to-rail output buffer.

The output voltage (full scale determined by reference) is given by:

2REF

CODE

0x1000

[V]

Where REF is the reference voltage and CODE is the digital input value in the range 0x000 to 0xFF0.Bits 3 to

0 must be set to zero. A power-on reset initially puts the internal latches to a defined state (all bits zero).

serial interface

A falling edge of CS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling

edges of SCLK. After 16 bits have been transferred or CS rises, the content of the shift register is moved to the

target latches (DAC A, DAC B, BUFFER, CONTROL), depending on the control bits within the data word.

Figure 13 shows examples of how to connect the TLV5626 to TMS320, SPI

™, and Microwire™.

TMS320

DSP FSX

CLKX

DX

TLV5626

SCLK

DIN

CS

SPI

I/O

SCK

MOSI

TLV5626

SCLK

DIN

CS

Microwire

I/O

SK

SO

TLV5626

SCLK

DIN

CS

Figure 13. Three-Wire Interface

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