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TLV5626IDG4 Datasheet(PDF) 6 Page - Texas Instruments |
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TLV5626IDG4 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 19 page ![]() TLV5626 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS236A –JUNE 1999 – REVISED JUNE 2000 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 digital input timing requirements MIN NOM MAX UNIT tsu(CS–CK) Setup time, CS low before first negative SCLK edge 10 ns tsu(C16-CS) Setup time, 16th negative SCLK edge (when D0 is sampled) before CS rising edge 10 ns twH SCLK pulse width high 25 ns twL SCLK pulse width low 25 ns tsu(D) Setup time, data ready before SCLK falling edge 10 ns th(D) Hold time, data held valid after SCLK falling edge 5 ns PARAMETER MEASUREMENT INFORMATION twL SCLK CS DIN D15 D14 D13 D12 D1 D0 X X 1 X 2 3 4 5 15 16 X twH tsu(D) th(D) tsu(CS-CK) tsu(C16-CS) Figure 1. Timing Diagram |
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