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ATTINY85-20SHR Datasheet(PDF) 10 Page - ATMEL Corporation |
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ATTINY85-20SHR Datasheet(HTML) 10 Page - ATMEL Corporation |
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10 / 29 page  10 ATtiny25/45/85 [DATASHEET] 2586PS–AVR–06/2013 SWAP Rd Swap Nibbles Rd(3..0) Rd(7..4),Rd(7..4)Rd(3..0) None 1 BSET s Flag Set SREG(s) 1 SREG(s) 1 BCLR s Flag Clear SREG(s) 0 SREG(s) 1 BST Rr, b Bit Store from Register to T T Rr(b) T 1 BLD Rd, b Bit load from T to Register Rd(b) TNone 1 SEC Set Carry C 1C 1 CLC Clear Carry C 0 C 1 SEN Set Negative Flag N 1N 1 CLN Clear Negative Flag N 0 N 1 SEZ Set Zero Flag Z 1Z 1 CLZ Clear Zero Flag Z 0 Z 1 SEI Global Interrupt Enable I 1I 1 CLI Global Interrupt Disable I 0 I 1 SES Set Signed Test Flag S 1S 1 CLS Clear Signed Test Flag S 0 S 1 SEV Set Twos Complement Overflow. V 1V 1 CLV Clear Twos Complement Overflow V 0 V 1 SET Set T in SREG T 1T 1 CLT Clear T in SREG T 0 T 1 SEH Set Half Carry Flag in SREG H 1H 1 CLH Clear Half Carry Flag in SREG H 0 H 1 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers Rd Rr None 1 MOVW Rd, Rr Copy Register Word Rd+1:Rd Rr+1:Rr None 1 LDI Rd, K Load Immediate Rd KNone 1 LD Rd, X Load Indirect Rd (X) None 2 LD Rd, X+ Load Indirect and Post-Inc. Rd (X), X X + 1 None 2 LD Rd, - X Load Indirect and Pre-Dec. X X - 1, Rd (X) None 2 LD Rd, Y Load Indirect Rd (Y) None 2 LD Rd, Y+ Load Indirect and Post-Inc. Rd (Y), Y Y + 1 None 2 LD Rd, - Y Load Indirect and Pre-Dec. Y Y - 1, Rd (Y) None 2 LDD Rd,Y+q Load Indirect with Displacement Rd (Y + q) None 2 LD Rd, Z Load Indirect Rd (Z) None 2 LD Rd, Z+ Load Indirect and Post-Inc. Rd (Z), Z Z+1 None 2 LD Rd, -Z Load Indirect and Pre-Dec. Z Z - 1, Rd (Z) None 2 LDD Rd, Z+q Load Indirect with Displacement Rd (Z + q) None 2 LDS Rd, k Load Direct from SRAM Rd (k) None 2 ST X, Rr Store Indirect (X) Rr None 2 ST X+, Rr Store Indirect and Post-Inc. (X) Rr, X X + 1 None 2 ST - X, Rr Store Indirect and Pre-Dec. X X - 1, (X) Rr None 2 ST Y, Rr Store Indirect (Y) Rr None 2 ST Y+, Rr Store Indirect and Post-Inc. (Y) Rr, Y Y + 1 None 2 ST - Y, Rr Store Indirect and Pre-Dec. Y Y - 1, (Y) Rr None 2 STD Y+q,Rr Store Indirect with Displacement (Y + q) Rr None 2 ST Z, Rr Store Indirect (Z) Rr None 2 ST Z+, Rr Store Indirect and Post-Inc. (Z) Rr, Z Z + 1 None 2 ST -Z, Rr Store Indirect and Pre-Dec. Z Z - 1, (Z) Rr None 2 STD Z+q,Rr Store Indirect with Displacement (Z + q) Rr None 2 STS k, Rr Store Direct to SRAM (k) Rr None 2 LPM Load Program Memory R0 (Z) None 3 LPM Rd, Z Load Program Memory Rd (Z) None 3 LPM Rd, Z+ Load Program Memory and Post-Inc Rd (Z), Z Z+1 None 3 SPM Store Program Memory (z) R1:R0 None IN Rd, P In Port Rd PNone 1 OUT P, Rr Out Port P Rr None 1 PUSH Rr Push Register on Stack STACK Rr None 2 POP Rd Pop Register from Stack Rd STACK None 2 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR Watchdog Reset (see specific descr. for WDR/Timer) None 1 BREAK Break For On-chip Debug Only None N/A Mnemonics Operands Description Operation Flags #Clocks |
Similar Part No. - ATTINY85-20SHR |
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Similar Description - ATTINY85-20SHR |
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