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LMX2531LQ1910E Datasheet(PDF) 7 Page - Texas Instruments

Part # LMX2531LQ1910E
Description  LMX2531 High Performance Frequency Synthesizer System with Integrated VCO
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

LMX2531LQ1910E Datasheet(HTML) 7 Page - Texas Instruments

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LMX2531
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SNAS252R – OCTOBER 2005 – REVISED FEBRUARY 2013
Electrical Characteristics (continued)
(VCC = 3.0 V, -40°C ≤ TA ≤ 85 °C; except as specified.)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Charge Pump
0.4 V < VCPout < 2.0 V
ICPoutV
Current vs. CP Voltage
4
%
TA = 25°C
Variation
CP Current vs. Temperature
ICPoutT
VCPout = 1.2 V
8
%
Variation
Normalized PLL 1/f Noise
ICP = 1X Charge Pump Gain
-94
LNPLL_flicker(10 kHz)
dBc/Hz
ICP = 16X Charge Pump Gain
-104
(2)
LN(f)
Normalized PLL Noise Floor
ICP = 1X Charge Pump Gain
-202
LNPLL_flat
dBc/Hz
ICP = 16X Charge Pump Gain
-212
(3)
VCO Frequencies
LMX2531LQ1146E
1106
1184
LMX2531LQ1226E
1184
1268
LMX2531LQ1312E
1268
1360
LMX2531LQ1415E
1360
1470
LMX2531LQ1500E
1499
1510
LMX2531LQ1515E
1450
1580
LMX2531LQ1570E
1530
1636
Operating Frequency Range
LMX2531LQ1650E
1590
1700
(All options have a frequency
fFout
divider, this applies before the
LMX2531LQ1700E
1662
1770
MHz
divider. The frequency after the
LMX2531LQ1742
1760
1866
divider is half of what is shown)
LMX2531LQ1778E
1726
1840
LMX2531LQ1910E
1834
2028
LMX2531LQ2080E
1904
2274
LMX2531LQ2265E
2178
2400
LMX2531LQ2570E
2336
2790
LMX2531LQ2820E
2710
2925
LMX2531LQ3010E
2910
3132
Other VCO Specifications
LMX2531LQ1742
65
Maximum Allowable
LMX2531LQ1500E/1570E/1650E/
Temperature Drift for
90
ΔTCL
1146E/1226/1312E/1415E/1515E
°C
Continuous Lock
LMX2531LQ1700E/1778E/1910E/
(4)
125
2080E/2265E/2570E/2820E/3010E
(2)
One of the specifications for modeling PLL in-band phase noise is the PLL 1/f noise normalized to 1 GHz carrier frequency and 10 kHz
offset, LPLL_flicker(10 kHz). From this normalized index of PLL 1/f noise, the PLL 1/f noise can be calculated for any carrier and offset
frequency as: LNPLL_flicker(f) = LPLL_flicker(10 kHz) - 10·log(10 kHz / f) + 20·log( Fout / 1 GHz ). Flicker noise can dominate at low offsets
from the carrier and has a 10 dB/decade slope and improves with higher charge pump currents and at higher offset frequencies . To
accurately measure LPLL_flicker(10 kHz) it is important to use a high phase detector frequency and a clean reference to make it such that
this measurement is on the 10 dB/decade slope close to the carrier. LPLL_flicker(f) can be masked by the reference oscillator performance
if a low power or noisy source is used. The total PLL in-band phase noise performance is the sum of LPLL_flicker(f) and LPLL_flat. In other
words,LPLL(f) = 10·log(10(
LN
PLL_flat
/ 10 ) + 10(LN
PLL_flicker
(f) / 10 )
(3)
A specification used for modeling PLL in-band phase noise floor is the Normalized PLL noise floor, LNPLL_flat, and is defined as:
LNPLL_flat = L(f) – 20·log(N) – 10·log(fPD). LPLL_flat is the single side band phase noise in a 1 Hz Bandwidth and fPD is the phase detector
frequency of the synthesizer. LPLL_flat contributes to the total noise, L(f). To measure LPLL_flat the offset frequency must be chosen
sufficiently smaller then the loop bandwidth of the PLL, and yet large enough to avoid a substantial noise contribution from the reference
and PLL flicker noise. LPLL_flat can be masked by the reference oscillator performance if a low power or noisy source is used. The total
PLL in-band phase noise performance is the sum of LPLL_flicker(f) and LPLL_flat. In other words,LPLL(f) = 10·log(10(
LN
PLL_flat
/ 10 ) + 10(LN
PLL_flicker
(f) / 10 )
(4)
Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was
at the time that the R0 register was last programmed, and still have the part stay in lock. The action of programming the R0 register,
even to the same value, activates a frequency calibration routine. This implies that the part will work over the entire frequency range, but
if the temperature drifts more than the maximum allowable drift for continuous lock, then it will be necessary to reload the R0 register to
ensure that it stays in lock. Regardless of what temperature the part was initially programmed at, the temperature can never drift outside
the frequency range of -40°C
≤TA≤ 85°C without violating specifications.
Copyright © 2005–2013, Texas Instruments Incorporated
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