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PBSS5230PAP Datasheet(PDF) 3 Page - NXP Semiconductors |
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PBSS5230PAP Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 17 page NXP Semiconductors PBSS5230PAP 30 V, 2 A PNP/PNP low VCEsat (BISS) transistor PBSS5230PAP All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved Product data sheet 11 January 2013 3 / 17 Symbol Parameter Conditions Min Max Unit IBM peak base current single pulse; tp ≤ 1 ms - -1 A [1] - 370 mW [2] - 570 mW [3] - 530 mW [4] - 700 mW [5] - 450 mW [6] - 760 mW [7] - 700 mW Ptot total power dissipation Tamb ≤ 25 °C [8] - 1450 mW Per device [1] - 510 mW [2] - 780 mW [3] - 730 mW [4] - 960 mW [5] - 620 mW [6] - 1040 mW [7] - 960 mW Ptot total power dissipation Tamb ≤ 25 °C [8] - 2000 mW Tj junction temperature - 150 °C Tamb ambient temperature -55 150 °C Tstg storage temperature -65 150 °C [1] Device mounted on an FR4 PCB, single-sided 35 µm copper strip line, tin-plated and standard footprint. [2] Device mounted on an FR4 PCB, single-sided 35 µm copper strip line, tin-plated, mounting pad for collector 1 cm2. [3] Device mounted on 4-layer PCB 35 µm copper strip line, tin-plated and standard footprint. [4] Device mounted on 4-layer PCB 35 µm copper strip line, tin-plated, mounting pad for collector 1 cm2. [5] Device mounted on an FR4 PCB, single-sided 70 µm copper strip line, tin-plated and standard footprint. [6] Device mounted on an FR4 PCB, single-sided 70 µm copper strip line, tin-plated, mounting pad for collector 1 cm2. [7] Device mounted on 4-layer PCB 70 µm copper strip line, tin-plated and standard footprint. [8] Device mounted on 4-layer PCB 70 µm copper strip line, tin-plated, mounting pad for collector 1 cm2. |
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