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LM5050-2 Datasheet(PDF) 5 Page - Texas Instruments |
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LM5050-2 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 22 page 0.0V 1.0V 0 mV VSD(REV) -500 mV VSD(REG) 200 mV VGATE VIN > VOUT VIN < VOUT tGATE(OFF) LM5050-2 www.ti.com SNVS679B – NOVEMBER 2010 – REVISED MARCH 2013 Electrical Characteristics (continued) Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the operating junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 12.0V, VOUT = 12.0V, VOFF= 0.0V, CGATE= 47 nF, and TJ = 25°C. Symbol Parameter Conditions Min Typ Max Unit OFF Pin VOUT = VIN-500 mV VOFF(IH) OFF Input High Threshold Voltage - 1.55 1.73 VOFF Rising V VOUT = VIN - 500 mV VOFF(IL) OFF Input Low Threshold Voltage 1.09 1.41 - VOFF Falling ΔVOFF OFF Threshold Voltage Hysteresis VOFF(IH) - VOFF(IL) - 160 - mV IOFF OFF Pin Internal Pull-down VOFF = 5.0V 2.0 5 8.0 µA nFGD Pin VOFF = 5V FET Test Threshold Voltage VSD(TST) VOUT = 12V 250 350 450 mV VIN < VOUT VIN falling from 12V ΔVSD(TST) FET Test Threshold Voltage Hysteresis - 95 - mV nFGD Output Low Voltage VOFF = 5V nFGDVOL - 630 850 mV nFGD Output = On InFGD = 1 mA Sinking nFGD Output Leakage Current VOFF = 0V nFGDIOL - 0.001 0.7 µA nFGD Output = Off VnFGD = 5.5V Figure 4. Gate Off Timing for Forward to Reverse Transition Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LM5050-2 |
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