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MAX9000 Datasheet(PDF) 18 Page - Altera Corporation |
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MAX9000 Datasheet(HTML) 18 Page - Altera Corporation |
18 / 46 page 18 Altera Corporation MAX 9000 Programmable Logic Device Family Data Sheet The output buffer in each IOC has an adjustable output slew rate that can be configured for low-noise or high-speed performance. A slower slew rate reduces board-level noise and adds a nominal timing delay to the output buffer delay (tOD) parameter. The fast slew rate should be used for speed-critical outputs in systems that are adequately protected against noise. Designers can specify the slew rate on a pin-by-pin basis during design entry or assign a default slew rate to all pins on a global basis. The slew rate control affects both rising and falling edges of the output signals. Output Configuration The MAX 9000 device architecture supports the MultiVolt I/O interface feature, which allows MAX 9000 devices to interface with systems of differing supply voltages. The 5.0-V devices in all packages can be set for 3.3-V or 5.0-V I/O pin operation. These devices have one set of VCC pins for internal operation and input buffers (VCCINT), and another set for I/O output drivers (VCCIO). The VCCINT pins must always be connected to a 5.0-V power supply. With a 5.0-V VCCINT level, input voltages are at TTL levels and are therefore compatible with 3.3-V and 5.0-V inputs. Table 6. Peripheral Bus Sources Peripheral Control Signal Source EPM9320 EPM9320A EPM9400 EPM9480 EPM9560 EPM9560A OE0/ENA0 Row C Row E Row F Row G OE1/ENA1 Row B Row E Row F Row F OE2/ENA2 Row ARow ERow ERow E OE3/ENA3 Row BRow BRow BRow B OE4/ENA4 Row ARow ARow ARow A OE5 Row DRow DRow DRow D OE6 Row CRow CRow CRow C OE7/CLR1 Row B/GOE Row B/GOE Row B/GOE Row B/GOE CLR0/ENA5 Row A/GCLR Row A/GCLR Row A/GCLR Row A/GCLR CLK0 GCLK1 GCLK1 GCLK1 GCLK1 CLK1 GCLK2 GCLK2 GCLK2 GCLK2 CLK2 Row DRow DRow DRow D CLK3 Row CRow CRow CRow C |
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