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C8051F570-IM Datasheet(PDF) 6 Page - Silicon Laboratories |
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C8051F570-IM Datasheet(HTML) 6 Page - Silicon Laboratories |
6 / 302 page C8051F55x/56x/57x 6 Rev. 1.1 21.2.2. Message Object Interface Registers ..................................................... 212 21.2.3. Message Handler Registers.................................................................. 212 21.2.4. CAN Register Assignment .................................................................... 213 22. SMBus................................................................................................................... 216 22.1. Supporting Documents .................................................................................. 217 22.2. SMBus Configuration..................................................................................... 217 22.3. SMBus Operation .......................................................................................... 217 22.3.1. Transmitter Vs. Receiver....................................................................... 218 22.3.2. Arbitration.............................................................................................. 218 22.3.3. Clock Low Extension............................................................................. 218 22.3.4. SCL Low Timeout.................................................................................. 218 22.3.5. SCL High (SMBus Free) Timeout ......................................................... 219 22.4. Using the SMBus........................................................................................... 219 22.4.1. SMBus Configuration Register.............................................................. 219 22.4.2. SMB0CN Control Register .................................................................... 223 22.4.3. Data Register ........................................................................................ 226 22.5. SMBus Transfer Modes................................................................................. 226 22.5.1. Write Sequence (Master) ...................................................................... 227 22.5.2. Read Sequence (Master) ...................................................................... 228 22.5.3. Write Sequence (Slave) ........................................................................ 229 22.5.4. Read Sequence (Slave) ........................................................................ 230 22.6. SMBus Status Decoding................................................................................ 230 23. UART0 ................................................................................................................... 233 23.1. Baud Rate Generator .................................................................................... 233 23.2. Data Format................................................................................................... 235 23.3. Configuration and Operation ......................................................................... 236 23.3.1. Data Transmission ................................................................................ 236 23.3.2. Data Reception ..................................................................................... 236 23.3.3. Multiprocessor Communications ........................................................... 237 24. Enhanced Serial Peripheral Interface (SPI0) ..................................................... 242 24.1. Signal Descriptions........................................................................................ 243 24.1.1. Master Out, Slave In (MOSI)................................................................. 243 24.1.2. Master In, Slave Out (MISO)................................................................. 243 24.1.3. Serial Clock (SCK) ................................................................................ 243 24.1.4. Slave Select (NSS) ............................................................................... 243 24.2. SPI0 Master Mode Operation ........................................................................ 244 24.3. SPI0 Slave Mode Operation .......................................................................... 246 24.4. SPI0 Interrupt Sources .................................................................................. 246 24.5. Serial Clock Phase and Polarity .................................................................... 247 24.6. SPI Special Function Registers ..................................................................... 248 25. Timers ................................................................................................................... 255 25.1. Timer 0 and Timer 1 ...................................................................................... 257 25.1.1. Mode 0: 13-bit Counter/Timer ............................................................... 257 25.1.2. Mode 1: 16-bit Counter/Timer ............................................................... 258 25.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload..................................... 258 |
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