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ML4819 Datasheet(PDF) 2 Page - Fairchild Semiconductor |
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ML4819 Datasheet(HTML) 2 Page - Fairchild Semiconductor |
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2 / 15 page  ML4819 2 REV. 1.0 10/10/2000 PIN CONFIGURATION PIN NAME FUNCTION PIN NAME FUNCTION 1 ISENSE A Input form the PFC current sense transformer to the PWM comparator (+). Current Limit occurs when this point reaches 5V. 2 OVP Input to Over-Voltage comparator. 3 GM OUT Output of Gain Modulator. A resistor to ground on this pin converts the current to a voltage. 4 EA OUT A Output of error amplifier. 5 INV A Inverting input to error amplifier. 6ISINE Current Multiplier input. 7 DUTY CYCLE PWM controller duty cycle is limited by setting this pin to a fixed voltage. 8 PWM B Error voltage feedback input. 9ISENSE B Input for Current Sense resistor for current mode operation or for Oscillator ramp for voltage mode operation. 10 RT Oscillator timing resistor pin. A 5V source across this resistor sets the charging current for CT 11 ILIM Cycle by cycle PWM current limit. Exceeding 1V threshold on this pin terminates the PWM cycle. 12 RAMP COMP Buffered output from the Oscillator Ramp (CT). A resistor to ground sets a current, 1/2 of which is sourced on pins 9 and 11. 13 GND B Return for the high current totem pole output of the PWM controller. 14 OUT B PWM controller totem pole output. 15 VCC Positive Supply for the IC. 16 OUT A PFC controller totem pole output. 17 GND A Return for the high current totem pole output of the PFC controller. 18 VREF Buffered output for the 5V voltage reference 19 GND Analog signal ground. 20 CT Timing Capacitor for the Oscillator. PIN DESCRIPTION ML4819 20-Pin PDIP ISENSE A OVP GM OUT EA OUT A INV A ISINE DUTY CYCLE PWM B ISENSE B RT CT GND VREF PGND A OUT A VCC OUT B PGND B RAMP COMP ILIM 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 TOP VIEW |
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Similar Description - ML4819 |
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