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ML4819 Datasheet(PDF) 5 Page - Fairchild Semiconductor

Part No. ML4819
Description  Power Factor and PWM Controller “Combo”
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Maker  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
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ML4819 Datasheet(HTML) 5 Page - Fairchild Semiconductor

 
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ML4819
REV. 1.0 10/10/2000
5
FUNCTIONAL DESCRIPTION
OSCILLATOR
The ML4819 oscillator charges the external capacitor (CT)
with a current (ISET) equal to 5/RSET. When the capacitor
voltage reaches the upper threshold, the comparator
changes state and the capacitor discharges to the lower
threshold through Q1. While the capacitor is discharging,
the clock provides a high pulse.
The oscillator period can be described by the following
relationship:
tOSC = tRAMP + tDEADTIME
where:
t=
C(Ramp Valley to Peak)
I
RAMP
SET
and:
t
C(Ramp Valley to Peak)
8.4mA - I
DEADTIME
SET
=
The maximum duty cycle of the PWM section can be
limited by setting a threshold on pin 7. when the CT ramp
is above the threshold at pin 7, the PWM output is held
off and the PWM flip-flop is set:
D
D
(V
- 0.9)
3.4
LIMIT
OSC
PIN7
×
where:
DLIMIT = Desired duty cycle limit
DOSC = Oscillator duty cycle
ELECTRICAL CHARACTERISTICS (Continued)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
UNDER-VOLTAGE LOCKOUT
Start-Up Threshold
15
16
17
V
Shut-Down Threshold
9
10
11
V
VREF Good Threshold
4.4
V
SUPPLY
Supply Current
Start-Up, VCC = 14V
0.6
1.2
mA
Operating, TJ = 25°C25
35
mA
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
Note 2: VCC is raised above the Start-Up Threshold first to activate the IC, then returned to 15V.
Note 3: PWM comparator bias currents are subtracted from this reading.
Figure 1. Oscillator Block Diagram
RT
ISET
CT
CLOCK
DUTY CYCLE
20
10
ISET
VREF
5V
+5V
TO PWM
LATCH B
TO PWM
LATCHES
8.4mA
Q1
CLOCK
tD
RAMP PEAK
RAMP VALLEY
CT
7
+
+


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