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MC908GR4CFAR2 Datasheet(PDF) 74 Page - Freescale Semiconductor, Inc |
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MC908GR4CFAR2 Datasheet(HTML) 74 Page - Freescale Semiconductor, Inc |
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74 / 408 page  Resets and Interrupts Technical Data MC68HC908GR8 — Rev 4.0 74 Resets and Interrupts MOTOROLA • Noise flag (NF) — NF is set when the SCI detects noise on incoming data or break characters, including start, data, and stop bits. The noise error interrupt enable bit, NEIE, enables NF to generate SCI error CPU interrupt requests. NF is in SCI status register 1. NEIE is in SCI control register 3. • Framing error bit (FE) — FE is set when a logic 0 occurs where the receiver expects a stop bit. The framing error interrupt enable bit, FEIE, enables FE to generate SCI error CPU interrupt requests. FE is in SCI status register 1. FEIE is in SCI control register 3. • Parity error bit (PE) — PE is set when the SCI detects a parity error in incoming data. The parity error interrupt enable bit, PEIE, enables PE to generate SCI error CPU interrupt requests. PE is in SCI status register 1. PEIE is in SCI control register 3. 4.4.2.9 KBD0–KBD4 Pins A logic 0 on a keyboard interrupt pin latches an external interrupt request. 4.4.2.10 ADC (Analog-to-Digital Converter) When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt after each ADC conversion. The COCO/IDMAS bit is not used as a conversion complete flag when interrupts are enabled. 4.4.2.11 TBM (Timebase Module) The timebase module can interrupt the CPU on a regular basis with a rate defined by TBR2–TBR0. When the timebase counter chain rolls over, the TBIF flag is set. If the TBIE bit is set, enabling the timebase interrupt, the counter chain overflow will generate a CPU interrupt request. Interrupts must be acknowledged by writing a logic 1 to the TACK bit. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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