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ML4812 Datasheet(PDF) 2 Page - Fairchild Semiconductor |
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ML4812 Datasheet(HTML) 2 Page - Fairchild Semiconductor |
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2 / 16 page  ML4812 2 REV. 1.0 10/10/2000 PIN CONFIGURATION PIN NAME FUNCTION 1 ISENSE Input from the current sense transformer to the non-inverting input of the PWM comparator. 2 GM OUT Output of gain modulator. A resistor to ground on this pin converts the current to a voltage. This pin is clamped to 5V and tied to the inverting input of the PWM comparator. 3 EA OUT Output of error amplifier. 4 EA– Inverting input to error amplifier. 5 OVP Input to over voltage comparator. 6 ISINE Current gain modulator input. 7 RAMP COMP Buffered output from the oscillator ramp (CT). A resistor to ground sets the current which is internally subtracted from the product of ISINE and IEA in the gain modulator. PIN NAME FUNCTION 8RT Oscillator timing resistor pin. A 5V source sets a current in the external resistor which is mirrored to charge CT. 9 CLOCK Digital clock output. 10 SHDN A TTL compatible low level on this pin turns off the output. 11 PWR GND Return for the high current totem pole output. 12 OUT High current totem pole output. 13 VCC Positive Supply for the IC. 14 VREF Buffered output for the 5V voltage reference. 15 GND Analog signal ground. 16 CT Timing capacitor for the oscillator. PIN DESCRIPTION 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ISENSE GM OUT EA OUT EA– OVP ISINE RAMP COMP RT CT GND VREF VCC OUT PWR GND SHDN CLOCK TOP VIEW ML4812 16-Pin PDIP (P16) TOP VIEW ML4812 20-Pin PLCC (Q20) EA OUT EA– NC OVP ISINE VREF VCC NC OUT PWR GND 4 5 6 7 8 18 17 16 15 14 32 1 20 19 910 11 12 13 |
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Similar Description - ML4812 |
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