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1500457 Datasheet(PDF) 18 Page - Freescale Semiconductor, Inc

Part No. 1500457
Description  Integrated Host Processor Hardware Specifications
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

1500457 Datasheet(HTML) 18 Page - Freescale Semiconductor, Inc

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MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
18
Freescale Semiconductor
DDR and DDR2 SDRAM
Table 19 provides the input AC timing specifications for the DDR SDRAM interface.
Figure 5 illustrates the DDR input timing diagram showing the tDISKEW timing parameter.
Figure 5. DDR Input Timing Diagram
Table 19. DDR and DDR2 SDRAM Input AC Timing Specifications
At recommended operating conditions with GVDD of (1.8 or 2.5 V) ± 5%.
Parameter
Symbol
Min
Max
Unit
Notes
Controller Skew for MDQS—MDQ/MECC/MDM
tCISKEW
ps
1, 2
400 MHz
–600
600
3
333 MHz
–750
750
266 MHz
–750
750
200 MHz
–750
750
Notes:
1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that
will be captured with MDQS[n]. This should be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW. This can be
determined by the equation: tDISKEW = ± (T/4 – abs (tCISKEW)); where T is the clock period and abs (tCISKEW) is the absolute
value of tCISKEW.
3. This specification applies only to the DDR interface.
MCK[n]
MCK[n]
tMCK
MDQ[x]
MDQS[n]
tDISKEW
D1
D0
tDISKEW


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