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1500457 Datasheet(PDF) 80 Page - Freescale Semiconductor, Inc |
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1500457 Datasheet(HTML) 80 Page - Freescale Semiconductor, Inc |
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80 / 87 page  MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 80 Freescale Semiconductor System Design Information 2. The e300 core PLL generates the core clock as a slave to the platform clock. The frequency ratio between the e300 core clock and the platform clock is selected using the e300 PLL ratio configuration bits as described in Section 19.2, “Core PLL Configuration.” 21.2 PLL Power Supply Filtering Each PLL gets power through independent power supply pins (AVDD1, AVDD2, respectively). The AVDD level should always equal to VDD, and preferably these voltages are derived directly from VDD through a low frequency filter scheme. There are a number of ways to provide power reliably to the PLLs, but the recommended solution is to provide four independent filter circuits as illustrated in Figure 42, one to each of the four AVDD pins. Independent filters to each PLL reduce the opportunity to cause noise injection from one PLL to the other. The circuit filters noise in the PLL resonant frequency range from 500 kHz to 10 MHz. It should be built with surface mount capacitors with minimum effective series inductance (ESL). Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a single large value capacitor. To minimize noise coupled from nearby circuits, each circuit should be placed as closely as possible to the specific AVDD pin being supplied. It should be possible to route directly from the capacitors to the AVDD pin, which is on the periphery of package, without the inductance of vias. Figure 42 shows the PLL power supply filter circuit. Figure 42. PLL Power Supply Filter Circuit 21.3 Decoupling Recommendations Due to large address and data buses and high operating frequencies, the MPC8349EA can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the MPC8349EA system, and the device itself requires a clean, tightly regulated source of power. Therefore, the system designer should place at least one decoupling capacitor at each VDD, OVDD, GVDD, and LVDD pin of the device. These capacitors should receive their power from separate VDD, OVDD, GVDD, LVDD, and GND power planes in the PCB, with short traces to minimize inductance. Capacitors can be placed directly under the device using a standard escape pattern. Others can surround the part. These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes. In addition, distribute several bulk storage capacitors around the PCB, feeding the VDD, OVDD, GVDD, and LVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should VDD AVDD (or L2AVDD) 2.2 µF 2.2 µF GND Low ESL Surface Mount Capacitors 10 Ω |
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