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1500457 Datasheet(PDF) 30 Page - Freescale Semiconductor, Inc

Part No. 1500457
Description  Integrated Host Processor Hardware Specifications
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

1500457 Datasheet(HTML) 30 Page - Freescale Semiconductor, Inc

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MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
30
Freescale Semiconductor
Ethernet: Three-Speed Ethernet, MII Management
8.2.4
RGMII and RTBI AC Timing Specifications
Table 31 presents the RGMII and RTBI AC timing specifications.
Table 31. RGMII and RTBI AC Timing Specifications
At recommended operating conditions with LVDD of 2.5 V ± 5%.
Parameter/Condition
Symbol1
Min
Typ
Max
Unit
Data to clock output skew (at transmitter)
tSKRGT
–0.5
0.5
ns
Data to clock input skew (at receiver)2
tSKRGT
1.0
2.8
ns
Clock cycle duration3
tRGT
7.2
8.0
8.8
ns
Duty cycle for 1000Base-T4, 5
tRGTH/tRGT
45
50
55
%
Duty cycle for 10BASE-T and 100BASE-TX3, 5
tRGTH/tRGT
40
50
60
%
Rise time (20%–80%)
tRGTR
0.75
ns
Fall time (80%–20%)
tRGTF
0.75
ns
Notes:
1. In general, the clock reference symbol for this section is based on the symbols RGT to represent RGMII and RTBI timing. For
example, the subscript of tRGT represents the TBI (T) receive (RX) clock. Also, the notation for rise (R) and fall (F) times
follows the clock symbol. For symbols representing skews, the subscript is SK followed by the clock being skewed (RGT).
2. This implies that PC board design requires clocks to be routed so that an additional trace delay of greater than 1.5 ns is added
to the associated clock signal.
3. For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.
4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet clock domains as long
as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed transitioned.
5. Duty cycle reference is LVDD/2.


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