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ML2036 Datasheet(PDF) 2 Page - Fairchild Semiconductor

Part No. ML2036
Description  Serial Input Programmable Sine Wave Generator with Digital Gain Control
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Maker  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
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ML2036 Datasheet(HTML) 2 Page - Fairchild Semiconductor

 
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ML2036
PRODUCT SPECIFICATION
2
REV. 1.0.2 7/26/01
Pin Configuration
Pin Description (Pin Number in Paranthesis is for SOIC Version)
PIN
NAME
FUNCTION
1 (2)
VSS
Negative supply (-5V).
2 (3)
PDN-INH
Three level input which controls the inhibit and power down modes. Current source pull-up
to VCC.
3 (4)
CLK
OUT 1
Digital clock output from the internal clock generator that can drive other devices at fCLK OUT
1 = fCLK IN/2.
4 (5)
CLK
OUT 2
Digital clock output from the internal clock generator that can drive other devices at fCLK OUT
2 = fCLK IN/8.
5 (6)
SCK
Serial clock. Digital input which clocks in serial data on its rising edges.
6 (7)
SID
Serial input data which programs the frequency of VOUT.
7 (8)
LATI
Digital input which latches serial data into the internal data latch on falling edges.
8 (9)
VCC
Positive supply (5V).
9 (10)
VREF
Reference input. The voltage on this pin determines the peak-to-peak swing of VOUT. VREF
can be tied to VCC.
10 (11)
VOUT
Analog output.
11 (12)
AGND
Analog ground. All analog inputs and outputs are referenced to this point.
12 (13)
DGND
Digital ground. All digital inputs and outputs are referenced to this point.
13 (15)
GAIN
Sets VOUT peak amplitude to VREF or VREF/2. Current source pull-down to DGND.
14 (16)
CLK IN
Clock input. The internal clock can be generated by tying a 3 to 12MHz crystal from this pin
to DGND, or by applying a digital clock signal directly to the pin.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VSS
PDN-INH
CLK OUT 1
CLK OUT 2
SCK
SID
LATI
CLK IN
GAIN
DGND
AGND
VOUT
VREF
VCC
TOP VIEW
ML2036
14-Pin PDIP (P14)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
TOP VIEW
ML2036
16-Pin Wide SOIC (S16W)
NC
VSS
PDN-INH
CLK OUT 1
CLK OUT 2
SCK
SID
LATI
CLK IN
GAIN
NC
DGND
AGND
VOUT
VREF
VCC


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