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3.3-VLVCMOS Datasheet(PDF) 15 Page - Altera Corporation |
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3.3-VLVCMOS Datasheet(HTML) 15 Page - Altera Corporation |
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15 / 34 page  Chapter 1: Cyclone III Device Datasheet 1–15 Switching Characteristics July 2012 Altera Corporation Cyclone III Device Handbook Volume 2 PLL Specifications Table 1–20 describes the PLL specifications for Cyclone III devices when operating in the commercial junction temperature range (0°C to 85°C), the industrial junction temperature range (–40°C to 100°C), and the automotive junction temperature range (–40°Cto 125°C). For more information about PLL block, refer to “PLL Block” in “Glossary” on page 1–27. Table 1–20. Cyclone III Devices PLL Specifications (1) (Part 1 of 2) Symbol Parameter Min Typ Max Unit fIN (2) Input clock frequency 5 — 472.5 MHz fINPFD PFD input frequency 5 — 325 MHz fVCO (3) PLL internal VCO operating range 600 — 1300 MHz fINDUTY Input clock duty cycle 40 — 60 % tINJITTER_CCJ (4) Input clock cycle-to-cycle jitter for FINPFD 100 MHz — — 0.15 UI Input clock cycle-to-cycle jitter for FINPFD < 100 MHz — — ±750 ps fOUT_EXT (external clock output) (2) PLL output frequency — — 472.5 MHz fOUT (to global clock) PLL output frequency (–6 speed grade) — — 472.5 MHz PLL output frequency (–7 speed grade) — — 450 MHz PLL output frequency (–8 speed grade) — — 402.5 MHz tOUTDUTY Duty cycle for external clock output (when set to 50%) 45 50 55 % tLOCK Time required to lock from end of device configuration — — 1 ms tDLOCK Time required to lock dynamically (after switchover, reconfiguring any non-post-scale counters/delays or areset is deasserted) —— 1 ms tOUTJITTER_PERIOD_DEDCLK (5) Dedicated clock output period jitter FOUT 100 MHz — — 300 ps FOUT < 100 MHz — — 30 mUI tOUTJITTER_CCJ_DEDCLK (5) Dedicated clock output cycle-to-cycle jitter FOUT 100 MHz — — 300 ps FOUT < 100 MHz — — 30 mUI tOUTJITTER_PERIOD_IO (5) Regular I/O period jitter FOUT 100 MHz — — 650 ps FOUT < 100 MHz — — 75 mUI tOUTJITTER_CCJ_IO (5) Regular I/O cycle-to-cycle jitter FOUT 100 MHz — — 650 ps FOUT < 100 MHz — — 75 mUI tPLL_PSERR Accuracy of PLL phase shift — — ±50 ps tARESET Minimum pulse width on areset signal. 10 — — ns tCONFIGPLL Time required to reconfigure scan chains for PLLs — 3.5 (6) — SCANCLK cycles |
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