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CAT93W66VP2I-GT3 Datasheet(PDF) 8 Page - ON Semiconductor |
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CAT93W66VP2I-GT3 Datasheet(HTML) 8 Page - ON Semiconductor |
8 / 16 page CAT93C66, CAT93W66 http://onsemi.com 8 Erase All Upon receiving an ERAL command (Figure 7), the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear cycle of all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the device can be determined by selecting the device and polling the DO pin. Once cleared, the contents of all memory bits return to a logical “1” state. Write All Upon receiving a WRAL command and data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN (Figure 8). The falling edge of CS will start the self clocking data write to all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the device can be determined by selecting the device and polling the DO pin. It is not necessary for all memory locations to be cleared before the WRAL command is executed. Figure 7. ERAL Instruction Timing SK CS DI DO STANDBY HIGH−Z HIGH−Z 10 1 BUSY READY STATUS VERIFY 00 tHZ tCS tSV tEW Figure 8. WRAL Instruction Timing STATUS VERIFY SK CS DI DO STANDBY HIGH−Z 10 1 BUSY READY 0 0 DN D0 tSV tHZ tCSMIN tEW |
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