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PIC10F220-I Datasheet(PDF) 25 Page - Microchip Technology |
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PIC10F220-I Datasheet(HTML) 25 Page - Microchip Technology |
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25 / 86 page  © 2007 Microchip Technology Inc. DS41270E-page 23 PIC10F220/222 TABLE 5-3: SUMMARY OF PORT REGISTERS 5.4 I/O Programming Considerations 5.4.1 BIDIRECTIONAL I/O PORTS Some instructions operate internally as read followed by write operations. The BCF and BSF instructions, for example, read the entire port into the CPU, execute the bit operation and re-write the result. Caution must be used when these instructions are applied to a port where one or more pins are used as input/outputs. For example, a BSF operation on bit 2 of GPIO will cause all eight bits of GPIO to be read into the CPU, bit 2 to be set and the GPIO value to be written to the output latches. If another bit of GPIO is used as a bidirectional I/O pin (say bit 0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the CPU and rewritten to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the Input mode, no problem occurs. However, if bit 0 is switched into Output mode later on, the content of the data latch may now be unknown. Example 5-1 shows the effect of two sequential Read-Modify-Write instructions (e.g., BCF, BSF, etc.) on an I/O port. A pin actively outputting a high or a low should not be driven from external devices at the same time in order to change the level on this pin (“wired-or”, “wired-and”). The resulting high output currents may damage the chip. EXAMPLE 5-1: I/O PORT READ-MODIFY- WRITE INSTRUCTIONS 5.4.2 SUCCESSIVE OPERATIONS ON I/O PORTS The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (Figure 5-5). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should allow the pin voltage to stabilize (load dependent) before the next instruction causes that file to be read into the CPU. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing this I/O port. FIGURE 5-5: SUCCESSIVE I/O OPERATION Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-On Reset Value on All Other Resets N/A TRISGPIO — — — — I/O Control Registers ---- 1111 ---- 1111 N/A OPTION GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 03h STATUS GPWUF — — TO PD Z DC C 0001 1xxx q00q quuu (1) 06h GPIO — — — — GP3 GP2 GP1 GP0 ---- xxxx ---- uuuu Legend: Shaded cells not used by PORT registers, read as ‘0’, – = unimplemented, read as ‘0’, x = unknown, u = unchanged, q = depends on condition. Note 1: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0. ;Initial GPIO Settings ;GPIO<3:2> Inputs ;GPIO<1:0> Outputs ; ; GPIO latch GPIO pins ; ---------- ---------- BCF GPIO, 1 ;---- pp01 ---- pp11 BCF GPIO, 0 ;---- pp10 ---- pp11 MOVLW 007h; TRIS GPIO ;---- pp10 ---- pp11 ; Note: The user may have expected the pin values to be ---- pp00. The second BCF caused GP1 to be latched as the pin value (High). PC PC + 1 PC + 2 PC + 3 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Instruction Fetched GP<2:0> MOVWF GPIO NOP Port pin sampled here NOP MOVF GPIO , W Instruction Executed MOVWF GPIO (Write to GPIO) NOP MOVF GPIO,W This example shows a write to GPIO followed by a read from GPIO. Data setup time = (0.25 TCY – TPD) where: TCY = instruction cycle TPD = propagation delay Therefore, at higher clock frequencies, a write followed by a read may be problematic. (Read GPIO) Port pin written here |
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