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93LC86TIP Datasheet(PDF) 11 Page - Microchip Technology |
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93LC86TIP Datasheet(HTML) 11 Page - Microchip Technology |
11 / 22 page 2010 Microchip Technology Inc. DS21131F-page 11 93LC76/86 4.0 PIN DESCRIPTIONS TABLE 4-1: PIN FUNCTION TABLE 4.1 Chip Select (CS) A high level selects the device. A low level deselects the device and forces it into Standby mode. However, a programming cycle which is already initiated will be completed, regardless of the CS input signal. If CS is brought low during a program cycle, the device will go into Standby mode as soon as the programming cycle is completed. CS must be low for 250 ns minimum (TCSL) between consecutive instructions. If CS is low, the internal control logic is held in a Reset status. 4.2 Serial Clock (CLK) The Serial Clock is used to synchronize the communi- cation between a master device and the 93LC76/86. Opcode, address and data bits are clocked in on the positive edge of CLK. Data bits are also clocked out on the positive edge of CLK. CLK can be stopped anywhere in the transmission sequence (at high or low level) and can be continued anytime with respect to clock high time (TCKH) and clock low time (TCKL). This gives the controlling master freedom in preparing opcode, address and data. CLK is a “don't care” if CS is low (device deselected). If CS is high, but Start condition has not been detected, any number of clock cycles can be received by the device without changing its status (i.e., waiting for Start condition). CLK cycles are not required during the self-timed WRITE (i.e., auto erase/write) cycle. After detection of a Start condition the specified number of clock cycles (respectively low-to-high transitions of CLK) must be provided. These clock cycles are required to clock in all opcode, address, and data bits before an instruction is executed (see Table 1-3 through Table 1-6 for more details). CLK and DI then become “don't care” inputs waiting for a new Start condition to be detected. 4.3 Data In (DI) Data In is used to clock in a Start bit, opcode, address and data synchronously with the CLK input. 4.4 Data Out (DO) Data Out is used in the Read mode to output data synchronously with the CLK input (TPD after the positive edge of CLK). This pin also provides Ready/Busy status information during erase and write cycles. Ready/Busy status infor- mation is available when CS is high. It will be displayed until the next Start bit occurs as long as CS stays high. 4.5 Organization (ORG) When ORG is connected to VCC, the x16 memory orga- nization is selected. When ORG is tied to VSS, the x8 memory organization is selected. There is an internal pull-up resistor on the ORG pin that will select x16 organization when left unconnected. 4.6 Program Enable (PE) This pin allows the user to enable or disable the ability to write data to the memory array. If the PE pin is floated or tied to VCC, the device can be programmed. If the PE pin is tied to VSS, programming will be inhibited. There is an internal pull-up on this device that enables programming if this pin is left floating. Name Function CS Chip Select CLK Serial Data Clock DI Serial Data Input DO Serial Data Output VSS Ground ORG Memory Configuration PE Program Enable VCC Power Supply Note: CS must go low between consecutive instructions, except when performing a sequential read (Refer to Section 3.1 “READ” for more detail on sequential reads). |
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