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AD7376ARWZ10 Datasheet(PDF) 14 Page - Analog Devices |
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AD7376ARWZ10 Datasheet(HTML) 14 Page - Analog Devices |
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14 / 20 page  AD7376 Rev. D | Page 14 of 20 DAISY-CHAIN OPERATION CS SDI SERIAL REGISTER D CK Q RS SHDN SDO RS CLK Figure 27. Detailed SDO Output Schematic of the AD7376 Figure 27 shows the details of the serial data output pin (SDO). SDO shifts out the SDI content in the previous frame; therefore, it can be used for daisy-chaining multiple devices. The SDO pin contains an open-drain N-Channel MOSFET and requires a pull-up resistor if the SDO function is used. Users need to tie the SDO pin of one package to the SDI pin of the next package. For example, in Figure 28, if two AD7376s are daisy-chained, a total of 14 bits of data are required for each operation. The first set of seven bits goes to U2; the second set of seven bits goes to U1. CS should be kept low until all 14 bits are clocked into their respective serial registers. Then CS is pulled high to complete the operation. When daisy-chaining multiple devices, users may need to increase the clock period because the pull-up resistor and the capacitive loading at the SDO to SDI interface may induce a time delay to subsequent devices. AD7376 SDO SDI CLK CS AD7376 SDO SDI CLK CS µC 5V RPU 2.2kΩ MOSI SS SCLK U1 U2 Figure 28. Daisy-Chain Configuration ESD PROTECTION All digital inputs are protected with a series input resistor and an ESD structure shown in Figure 29. These structures apply to digital input pins CS, CLK, SDI, RS, and SHDN. INPUT 340Ω LOGIC PINS VDD GND Figure 29. Equivalent ESD Protection Circuit All analog terminals are also protected by ESD protection diodes, as shown in Figure 30. VSS VDD A W B Figure 30. Equivalent ESD Protection Analog Pins TERMINAL VOLTAGE OPERATING RANGE The AD7376 VDD and VSS power supplies define the boundary conditions for proper 3-terminal digital potentiometer oper- ation. Applied signals present on Terminals A, B, and W that are more positive than VDD or more negative than VSS will be clamped by the internal forward-biased diodes (see Figure 30). POWER-UP AND POWER-DOWN SEQUENCES Because of the ESD protection diodes that limit the voltage compliance at Terminals A, B, and W (see Figure 30), it is important to power VDD/VSS before applying voltage to Terminals A, B, and W. Otherwise, the diodes are forward biased such that VDD/VSS are powered unintentionally and affect the system. Similarly, VDD/VSS should be powered down last. The ideal power-up sequence is in the following order: GND, VDD, VSS, digital inputs, and VA/VB/VW. The order of powering VA, VB, VW, and the digital inputs is not important, as long as they are powered after VDD/VSS. |
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