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AD5662ARJ-1REEL7 Datasheet(PDF) 17 Page - Analog Devices

Part # AD5662ARJ-1REEL7
Description  16-Bit nanoDAC in a SOT-23
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD5662ARJ-1REEL7 Datasheet(HTML) 17 Page - Analog Devices

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AD5662
Rev. A | Page 17 of 24
AD5662 to 80C51/80L51 Interface
AD5662 to MICROWIRE Interface
Figure 39 shows a serial interface between the AD5662 and the
80C51/80L51 microcontroller. The setup for the interface is as
follows. TxD of the 80C51/80L51 drives SCLK of the AD5662,
while RxD drives the serial data line of the part. The SYNC
signal is again derived from a bit-programmable pin on the port.
In this case, port line P3.3 is used. When data is to be transmitted
to the AD5662, P3.3 is taken low. The 80C51/80L51 transmits
data in 8-bit bytes only; thus only eight falling clock edges occur
in the transmit cycle. To load data to the DAC, P3.3 is left low
after the first eight bits are transmitted, and a second write cycle
is initiated to transmit the second byte of data. P3.3 is taken
high following the completion of this cycle. The 80C51/80L51
outputs the serial data in a format that has the LSB first. The
AD5662 must receive data with the MSB first. The 80C51/80L51
transmit routine should take this into account.
Figure 40 shows an interface between the AD5662 and any
MICROWIRE-compatible device. Serial data is shifted out on
the falling edge of the serial clock and is clocked into the AD5662
on the rising edge of the SK.
MICROWIRE*
AD5662*
*ADDITIONAL PINS OMITTED FOR CLARITY
CS
SK
SO
SYNC
SCLK
DIN
Figure 40. AD5662 to MICROWIRE Interface
80C51/80L51*
AD5662*
*ADDITIONAL PINS OMITTED FOR CLARITY
P3.3
TxD
RxD
SYNC
SCLK
DIN
Figure 39. AD5662 to 80C51/80L51 Interface


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