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H5TQ1G63DFRRDC Datasheet(PDF) 14 Page - Hynix Semiconductor |
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H5TQ1G63DFRRDC Datasheet(HTML) 14 Page - Hynix Semiconductor |
14 / 34 page Rev. 1.7 /Sep. 2011 14 Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns Table 2 -Basic IDD and IDDQ Measurement Conditions Symbol DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 DDR3-2133 Unit 7-7-7 9-9-9 11-11-11 13-13-13 14-14-14 tCK 1.875 1.5 1.25 1.07 0.935 ns CL 7 9 11 13 14 nCK nRCD 7 9 11 13 14 nCK nRC 27 33 39 45 50 nCK nRAS 20 24 28 32 36 nCK nRP 7 9 11 13 14 nCK nFAW 1KB page size 20 20 24 26 27 nCK 2KB page size 27 30 32 33 38 nCK nRRD 1KB page size 4 4 5 5 6 nCK 2KB page size 6 5 6 6 7 nCK nRFC -512Mb 48 60 72 85 97 nCK nRFC-1 Gb 59 74 88 103 118 nCK nRFC- 2 Gb 86 107 128 150 172 nCK nRFC- 4 Gb 160 200 240 281 321 nCK nRFC- 8 Gb 187 234 280 328 375 nCK Symbol Description IDD0 Operating One Bank Active-Precharge Current CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT and PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 3; Data IO: MID-LEVEL; DM: stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 3); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 3. IDD1 Operating One Bank Active-Read-Precharge Current CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT, RD and PRE; Command, Address; Bank Address Inputs, Data IO: partially toggling according to Table 4; DM: stable at 0; Bank Activity: Cycling with on bank active at a time: 0,0,1,1,2,2,... (see Table 4); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 4. |
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