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H5TQ1G63DFRG7C Datasheet(PDF) 29 Page - Hynix Semiconductor |
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H5TQ1G63DFRG7C Datasheet(HTML) 29 Page - Hynix Semiconductor |
29 / 34 page Rev. 1.7 /Sep. 2011 29 DDR3-1600 Speed Bins For specific Notes See "" on page 32. Speed Bin DDR3-1600 PB Unit Note CL - nRCD - nRP 11-11-11 Parameter Symbol min max Internal read command to first data tAA 13.75 20 ns ACT to internal read or write delay time tRCD 13.75 — ns PRE command period tRP 13.75 — ns ACT to ACT or REF command period tRC 48.75 — ns ACT to PRE command period tRAS 35 9 * tREFI ns CL = 5 CWL = 5 tCK(AVG) 3.0 3.3 ns 1,2,3,4,8, 10,11 CWL = 6, 7, 8 tCK(AVG) Reserved ns 4 CL = 6 CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3,8 CWL = 6 tCK(AVG) Reserved ns 1,2,3,4,8 CWL = 7, 8 tCK(AVG) Reserved ns 4 CL = 7 CWL = 5 tCK(AVG) Reserved ns 4 CWL = 6 tCK(AVG) 1.875 < 2.5 ns 1,2,3,4,8 (Optional) Note 5,11 CWL = 7 tCK(AVG) Reserved ns 1,2,3,4,8 CWL = 8 tCK(AVG) Reserved ns 4 CL = 8 CWL = 5 tCK(AVG) Reserved ns 4 CWL = 6 tCK(AVG) 1.875 < 2.5 ns 1,2,3,8 CWL = 7 tCK(AVG) Reserved ns 1,2,3,4,8 CWL = 8 tCK(AVG) Reserved ns 1,2,3,4 CL = 9 CWL = 5, 6 tCK(AVG) Reserved ns 4 CWL = 7 tCK(AVG) 1.5 <1.875 ns 1,2,3,4,8 (Optional) Note 5,11 CWL = 8 tCK(AVG) Reserved ns 1,2,3,4 CL = 10 CWL = 5, 6 tCK(AVG) Reserved ns 4 CWL = 7 tCK(AVG) 1.5 <1.875 ns 1,2,3,8 CWL = 8 tCK(AVG) Reserved ns 1,2,3,4 CL = 11 CWL = 5, 6,7 tCK(AVG) Reserved ns 4 CWL = 8 tCK(AVG) 1.25 <1.5 ns 1,2,3 Supported CL Settings 5,6,(7),8,(9),10,11 nCK Supported CWL Settings 5, 6, 7, 8 nCK |
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