Electronic Components Datasheet Search |
|
H5TQ1G63DFR-11C Datasheet(PDF) 46 Page - Hynix Semiconductor |
|
H5TQ1G63DFR-11C Datasheet(HTML) 46 Page - Hynix Semiconductor |
46 / 172 page Rev. 1.1 /Jan. 2011 46 1.4.3.6 Output Disable The DDR3 SDRAM outputs may be enabled/disabled by MR1 (bit A12) as shown in Figure 9. When this feature is enabled (A12=1), all output pins (DQs, DQS, DQS, etc.) are disconnected from the device, thus removing any loading of the output drivers. This feature may be useful when measuring module power, for example. For normal operation, A12 should be set to ‘0’. |
Similar Part No. - H5TQ1G63DFR-11C |
|
Similar Description - H5TQ1G63DFR-11C |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |