H5TQ1G63DFR-11C datasheet(90/172 Pages) HYNIX

Part #	H5TQ1G63DFR-11C

Description	1Gb DDR3 SDRAM

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Manufacturer	HYNIX [Hynix Semiconductor]

Direct Link	http://www.skhynix.com/kor/main.do

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90 / 172 page

Rev. 1.1 /Jan. 2011

90

Figure 49. WRITE (BC4) OTF to PRECHARGE Operation

Figure 50. WRITE (BL8) to WRITE (BL8)

ADDRESS4

DQS, DQS#

tWPST

DQ2

Din

n

TRANSITIONING DATA

DON’T CARE

Bank.

Col n

Din

n+1

Din

n+2

Din

n+3

NOTE: 1. BC4 OTF, WL=5 (CWL = 5, AL = 0)

2. Din n (or b) = data-in from column n

3. NOP commands are shown for ease of illustration; other commands may be valid at these times.

4. BC4 OTF setting activated by MR0[A1:0 = 01] and A12 = 0 during WRITE command at T0.

5. The write recovery time(tWR) starts at the rising clock edge T9 (4 clocks from T5).

4 clocks

T0

CK#

CK

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

Ta0

Ta1

T14

COMMAND3

VALID

tWR5

WL = 5

tWPRE

NOP

WRITE

NOP

T0

CK#

CK

COMMAND3

ADDRESS4

DQS, DQS#

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

NOP

tWPRE

tWPST

DQ2

WL=5

Din

n

TRANSITIONING DATA

DON’T CARE

T11

T12

T13

T14

WRITE

NOP

Bank.

Col n

Din

n+5

Din

n+6

Din

n+7

Din

n+1

Din

n+2

Din

n+3

Din

n+4

Bank.

Col b

tWTR

READ

RL=5

NOTE: 1. RL=5 (CL=5, AL=0), WL=5(CWL=5, AL=0)

2. Din n = data-in from column n; Dout b= data-out from column b.

3. NOP commands are shown for ease of illustration; other commands may be valid at these times.

4. BL8 setting activated by either MR0[A1:0=00] or MR0[A1:0=01] and A12=1 during WRITE command at T0.

READ command at T11 can be either BC4 or BL8 depending on MR0[A1:0] and A12 status at T13.

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