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HMT41GV7MFR8A Datasheet(PDF) 35 Page - Hynix Semiconductor |
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HMT41GV7MFR8A Datasheet(HTML) 35 Page - Hynix Semiconductor |
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35 / 67 page  Rev. 1.0 / Aug. 2012 35 Single Ended Output Slew Rate When the Reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for single ended signals are shown in table and figure below. Notes: 1. Output slew rate is verified by design and characterisation, and may not be subject to production test. Single Ended Output slew Rate Definition Description: SR; Slew Rate Q: Query Output (like in DQ, which stands for Data-in, Query-Output) se: Single-ended Signals For Ron = RZQ/7 setting Note 1): In two cases, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane. Case 1 is a defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low or low to high) while all remaining DQ signals in the same byte lane are static (i.e. they stay at either high or low). Case 2 is a defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low or low to high) while all remaining DQ signals in the same byte lane switching into the opposite direction (i.e. from low to high of high to low respectively). For the remaining DQ signal switching in to the opposite direction, the regular maximum limite of 5 V/ns applies. Single-ended Output slew Rate Definition Description Measured Defined by From To Single-ended output slew rate for rising edge VOL(AC) VOH(AC) [VOH(AC)-VOL(AC)] / DeltaTRse Single-ended output slew rate for falling edge VOH(AC) VOL(AC) [VOH(AC)-VOL(AC)] / DeltaTFse Output Slew Rate (single-ended) DDR3L-800 DDR3L-1066 DDR3L-1333 Units Parameter Symbol Min Max Min Max Min Max Single-ended Output Slew Rate SRQse 1.75 51) 1.75 51) 1.75 51) V/ns Delta TFse Delta TRse vOH(AC) vOl(AC) V∏ Single Ended Output Slew Rate Definition |
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