HMT42GR7AFR4A datasheet(10/72 Pages) HYNIX

Part #	HMT42GR7AFR4A

Description	DDR3L SDRAM Registered DIMM Based on 4Gb A-die

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Manufacturer	HYNIX [Hynix Semiconductor]

Direct Link	http://www.skhynix.com/kor/main.do

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10 / 72 page

Rev. 0.1 / Jul. 2012

10

Registering Clock Driver Specifications

Capacitance Values

Input & Output Timing Requirements

Symbol

Parameter

Conditions

Min

Typ Max

Unit

CI

Input capacitance, Data inputs

1.5

-

2.5

pF

Input capacitance, CK, CK, FBIN, FBIN

(up to DDR3-1600)

1.5

-

2.5

pF

CIR

Input capacitance, RESET, MIRROR,

QCSEN

VI = VDD or GND; VDD = 1.5v

--

3

pF

Symbol

Parameter

Conditions

DDR3L-800

1066/1333

DDR3L-1600

DDR3L-1866

Unit

Min

Max

Min

Max

Min

Max

fclock

Input clock fre-

quency

Application fre-

quency

300

670

300

810

300

945

Mhz

fTEST

Input clock fre-

quency

Test frequency

70

300

70

300

70

300

Mhz

tSU

Setup time

Input valid before

CK/CK

100

-

50

-

40

-

ps

tH

Hold time

Input to remain

valid after CK/CK

175-125-

75

-

ps

tPDM

Propagation

delay, single-bit

switching

CK/CK to output

0.65

1.0

0.65

1.0

0.65

1.0

ns

tDIS

Output disable

time (1/2-Clock

prelaunch)

Yn/Yn to output

float

0.5 +

tQSK1(min)

-

0.5 +

tQSK1(min)

-

0.5 +

tQSK1(min)

-ps

tEN

Output enable

time (1/2-Clock

prelaunch)

Output driving to

Yn/Yn

0.5 -

tQSK1(max)

-

0.5 -

tQSK1(max)

-

0.5 -

tQSK1(max)

-ps

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HMT42GR7AFR4A Datasheet(PDF) 10 Page - Hynix Semiconductor

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