DQ

(R/W1)

DQ

(R/W0)

DQ

(BREAK)

t

(STRH)

t

(STRB)

t

(DSU)

t

(SSU)

t

,t

(CYCB)

(B)

t

(DH)

t

(SH)

t

(DV)

t

(BR)

t

(SV)

T0269-01

bq34z950

SLUSBF0A – APRIL 2013 – REVISED MAY 2013

www.ti.com

DQ 1-WIRE INTERFACE

DQ TIMING SPECIFICATIONS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Cycle time, host to bq34z950

3

ms

Cycle time, bq34z950 to host

3

6

ms

Start hold, host to bq34z950

5

ns

Start hold, bq34z950 to host

500

750

μs

Data setup

μs

Data hold

750

μs

Data valid

1.5

ms

Stop setup

2.25

ms

Stop hold

700

μs

Stop valid

2.95

ms

Break

3

ms

Break recovery

1

ms

(1)

interface is not used.

Figure 2. DQ Timing Diagram

DQ timing for this device is selectable by adjusting values in Data Flash Sub Class 0x113. See Figure 3 for an

overview of the flash values.

12

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