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SST25VF016B Datasheet(PDF) 11 Page - Silicon Storage Technology, Inc |
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SST25VF016B Datasheet(HTML) 11 Page - Silicon Storage Technology, Inc |
11 / 32 page ©2011 Silicon Storage Technology, Inc. DS25044A 08/11 11 16 Mbit SPI Serial Flash SST25VF016B Data Sheet A Microchip Technology Company High-Speed-Read (80 MHz) The High-Speed-Read instruction supporting up to 80 MHz Read is initiated by executing an 8-bit com- mand, 0BH, followed by address bits [A23-A0] and a dummy byte. CE# must remain active low for the duration of the High-Speed-Read cycle. See Figure 6 for the High-Speed-Read sequence. Following a dummy cycle, the High-Speed-Read instruction outputs the data starting from the speci- fied address location. The data output stream is continuous through all addresses until terminated by a low to high transition on CE#. The internal address pointer will automatically increment until the high- est memory address is reached. Once the highest memory address is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address space. Once the data from address location 1FFFFFH has been read, the next output will be from address location 000000H. Figure 6: High-Speed-Read Sequence Byte-Program The Byte-Program instruction programs the bits in the selected byte to the desired data. The selected byte must be in the erased state (FFH) when initiating a Program operation. A Byte-Program instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of the Byte-Program instruction. The Byte-Program instruction is initiated by executing an 8-bit command, 02H, followed by address bits [A23-A0]. Following the address, the data is input in order from MSB (bit 7) to LSB (bit 0). CE# must be driven high before the instruction is exe- cuted. The user may poll the Busy bit in the software status register or wait TBP for the completion of the internal self-timed Byte-Program operation. See Figure 7 for the Byte-Program sequence. Figure 7: Byte-Program Sequence 1271 HSRdSeq.0 CE# SO SI SCK ADD. 012 34 5 6 7 8 ADD. ADD. 0B HIGH IMPEDANCE 15 16 23 24 31 32 39 40 47 48 55 56 63 64 N+2 N+3 N+4 N N+1 X MSB MSB MSB MODE 0 MODE 3 DOUT DOUT DOUT DOUT 80 71 72 DOUT Note: X = Dummy Byte: 8 Clocks Input Dummy Cycle (VIL or VIH) 1271 ByteProg.0 CE# SO SI SCK ADD. 01 2 3 4 5 6 7 8 ADD. ADD. DIN 02 HIGH IMPEDANCE 15 16 23 24 31 32 39 MODE 0 MODE 3 MSB MSB MSB LSB |
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