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DSPIC33FJ06GS101 Datasheet(PDF) 10 Page - Microchip Technology |
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DSPIC33FJ06GS101 Datasheet(HTML) 10 Page - Microchip Technology |
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10 / 20 page  dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 DS80439M-page 10 2009-2013 Microchip Technology Inc. 23. Module: UART The UART error interrupt may not occur, or may occur at an incorrect time, if multiple errors occur during a short period of time. Work around Read the error flags in the UxSTA register whenever a byte is received to verify the error status. In most cases, these bits will be correct, even if the UART error interrupt fails to occur. Affected Silicon Revisions 24. Module: I2C When the I2C module is configured as a 10-bit slave with an address of 0x102, the I2CxRCV register content for the lower address byte is 0x01 rather than 0x02; however, the module acknowledges both address bytes. Work around None. Affected Silicon Revisions 25. Module: I2C In 10-bit Addressing mode, some address matches do not set the RBF flag or load the receive register I2CxRCV, if the lower address byte matches the reserved addresses. In particular, these include all addresses with the form XX0000XXXX and XX1111XXXX, with the following exceptions: • 001111000X • 011111001X • 101111010X • 111111011X Work around Ensure that the lower address byte in 10-bit Addressing mode does not match any 7-bit reserved addresses. Affected Silicon Revisions 26. Module: PSV Operations An address error trap occurs in certain addressing modes when accessing the first four bytes of an PSV page. This occurs only when using the following addressing modes: • MOV.D • Register Indirect Addressing (Word or Byte mode) with pre/post-decrement Work around Do not perform PSV accesses to any of the first four bytes using the above addressing modes. For applications using the C language, MPLAB C30 Version 3.11 or higher, provides the following command-line switch that implements a work around for the erratum. -merrata=psv_trap Refer to the readme.txt file in the MPLAB C30 v3.11 toolsuite for further details. Affected Silicon Revisions 27. Module: Comparator The comparator fails to wake the CPU from Sleep mode when the internal voltage reference is used (i.e., the EXTREF bit is set to ‘0’). Work around Use the external reference source by setting the EXTREF bit to ‘1’. Affected Silicon Revisions 28. Module: PWM When multiple PWM channels are operating in Independent Time Base mode (ITB = 1) and the frequency is being updated on the fly, PWM channels configured for Push-Pull mode may not remain synchronized with other PWM output modes. Work around When multiple PWM channels are operating in Independent Time Base mode, immediate updates to the PWM module (IUE = 1) must be enabled for PWM channels to remain synchronized. Affected Silicon Revisions A2 A3 A4 XX X A2 A3 A4 XX X A2 A3 A4 XX X A2 A3 A4 XX X A2 A3 A4 XX X A2 A3 A4 XX X |
Similar Part No. - DSPIC33FJ06GS101_13 |
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Similar Description - DSPIC33FJ06GS101_13 |
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