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HMT325V7CFR8A Datasheet(PDF) 30 Page - Hynix Semiconductor |
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HMT325V7CFR8A Datasheet(HTML) 30 Page - Hynix Semiconductor |
30 / 68 page Rev. 1.0 / Aug. 2012 30 Single-ended requirements for differential signals Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, of DQSU) has also to comply with certain requirements for single-ended signals. CK and CK have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels (VIH (ac) / VIL (ac)) for ADD/CMD signals) in every half-cycle. DQS, DQSL, DQSU, DQS, DQSL have to reach VSEHmin / VSELmax (approximately the ac-levels (VIH (ac) / VIL (ac)) for DQ signals) in every half-cycle preceding and following a valid transition. Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g., if VIH.CA(AC150)/VIL.CA(AC150) is used for ADD/CMD signals, then these ac-levels apply also for the single- ended signals CK and CK. Single-ended requirements for differential signals. Note that, while ADD/CMD and DQ signal requirements are with respect to Vref, the single-ended compo- nents of differential signals have a requirement with respect to VDD / 2; this is nominally the same. the transition of single-ended signals through the ac-levels is used to measure setup time. For single-ended components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing, but adds a restriction on the common mode characteristics of these signals. VDD or VDDQ VSEHmin VDD/2 or VDDQ/2 VSEH VSELmax VSS or VSSQ CK or DQS VSEL time |
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