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AZP53PG Datasheet(PDF) 4 Page - Arizona Microtek, Inc |
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AZP53PG Datasheet(HTML) 4 Page - Arizona Microtek, Inc |
4 / 13 page Arizona Microtek, Inc. AZP53 Low Phase Noise Sine Wave/CMOS to LVPECL Buffer/Translator www.azmicrotek.com +1-480-962-5881 4 Request a Sample Mar 2013, Rev 2.2 Figure 2- S11, Parameters, D Input INPUT TERMINATION The D input bias is VDD/2 fed through an internal 10kΩ resistor. For clock applications, an input signal of at least 750mVpp ensures the AZP53 meets AC specifications. The input should also be AC coupled to maintain a 50% duty cycle on the outputs. The input can be driven to any voltage between 0V and VDD without damage or waveform degradation. D VDD/2 10k Ω Input signal A/R Figure 3 - Input Termination |
Similar Part No. - AZP53PG |
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Similar Description - AZP53PG |
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