Integrated Silicon Solution, Inc. — www.issi.com

1

Rev. D

08/16/2012

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IS43/46DR83200A

IS43/46DR16160A

AUGUST 2012

32Mx8, 16Mx16 DDR2 DRAM

FEATURES

• JEDEC standard 1.8V I/O (SSTL_18-compatible)

• Double data rate interface: two data transfers

per clock cycle

• Differential data strobe (DQS, DQS)

• 4-bit prefetch architecture

• On chip DLL to align DQ and DQS transitions

with CK

• 4 internal banks for concurrent operation

• Programmable CAS latency (CL) 3, 4, 5, and 6

supported

• Posted CAS and programmable additive latency

(AL) 0, 1, 2, 3, 4, and 5 supported

• WRITE latency = READ latency - 1 tCK

• Programmable burst lengths: 4 or 8

• Adjustable data-output drive strength, full and

reduced strength options

• On-die termination (ODT)

OPTIONS

• Configuration(s):

32Mx8 (8Mx8x4 banks) IS43/46DR83200A

16Mx16 (4Mx16x4 banks) IS43/46DR16160A

• Package:

x8: 60-ball TW-BGA (8mm x 10.5mm)

x16: 84-ball TW-BGA (8mm x 12.5mm)

Timing – Cycle time

2.5ns @CL=6 DDR2-800E

3.0ns @CL=5 DDR2-667D

3.75ns @CL=4 DDR2-533C

5.0ns @CL=3 DDR2-400B

• Temperature Range:

Commercial (0°C ≤ Tc ≤ 85°C)

DESCRIPTION

ISSI's 256Mb DDR2 SDRAM uses a double-data-rate

architecture to achieve high-speed operation. The

double-data rate architecture is essentially a 4n-prefetch

architecture, with an interface designed to transfer two

data words per clock cycle at the I/O balls.

Parameter

32M x 8

16M x 16

Configuration

8M x 8 x 4

banks

4M x 16 x 4

banks

Refresh Count

8K/64ms

8K/64ms

Row Addressing

8K (A0-A12) 8K (A0-A12)

Column

Addressing

1K (A0-A9)

512 (A0-A8)

Bank Addressing BA0, BA1

BA0, BA1

Precharge

Addressing

A10

A10

ADDRESS TABLE

Speed Grade

-25E

-3D

-37C

-5B

tRCD

15

15

15

15

tRP

15

15

15

15

tRC

60

60

60

55

tRAS

45

45

45

40

tCK @CL=3

5

5

5

5

tCK @CL=4

3.75

3.75

3.75

5

tCK @CL=5

3

3

—

—

tCK @CL=6

2.5

—

—

—

KEY TIMING PARAMETERS