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MIC24420 Datasheet(PDF) 23 Page - Micrel Semiconductor
MICREL [Micrel Semiconductor]
MIC24420 Datasheet(HTML) 23 Page - Micrel Semiconductor
/ 34 page
PCB Layout Guidelines
Warning!!! To minimize EMI and output noise, follow
these layout recommendations.
PCB Layout is critical to achieve reliable, stable and
efficient performance. A ground plane is required to
control EMI and minimize the inductance in power,
signal and return paths.
The following guidelines should be followed to insure
proper operation of the MIC24420/MIC24421 converter.
Place the IC and the external Low-side MOSFET
close to the point of load (POL).
Use fat traces to route the input and output power
The exposed pad (EP) on the bottom of the IC must
be connected to the ground.
Use several vias to connect the EP to the ground
plane on layer 2.
Signal and power grounds should be kept separate
and connected at only one location, the EP ground
of the package.
The following signals and their components should
be decoupled or referenced to the power ground
plane: VIND1, VIND2, PVDD, PGND1, PGND2,
LSD1, and LSD2.
These analog signals should be referenced or
decoupled to the analog ground plane: VIN,
EN/DLY1, EN/DLY2, COMP1, COMP2, FB1, and
Place the overcurrent sense resistor close to the
CS1 or CS2 pins. The trace coming from the switch
node to this resistor has high dv/dt and should be
routed away from other noise sensitive components
and traces. Avoid routing this trace under the
inductor to prevent noise from coupling into the
Place the input capacitor next. Ceramic capacitors
must be placed between VIND1 and PGND1 and
between VIND2 and PGND2.
Place the input capacitors on the same side of the
board and as close to the IC and low-side MOSFET
Keep both the VIN and PGND connections short.
Place several vias to the ground plane close to the
input capacitor ground terminal, but not between the
input capacitors and IC pins.
Use either X7R or X5R dielectric input capacitors.
Do not use Y5V or Z5U type capacitors.
Do not replace the ceramic input capacitor with any
other type of capacitor. Any type of capacitor can be
placed in parallel with the input capacitor.
If a Tantalum input capacitor is placed in parallel
with the input capacitor, it must be recommended for
switching regulator applications and the operating
voltage must be derated by 50%.
In “Hot-Plug” applications, a Tantalum or Electrolytic
bypass capacitor must be used to limit the over-
voltage spike seen on the input supply with power is
suddenly applied. The value must be sufficiently
large to prevent this voltage spike from exceeding
An additional Tantalum or Electrolytic bypass input
capacitor of 22µF or higher is required at the input
Keep the inductor connection to the switch node
Do not route any digital or analog signal lines
underneath or close to the inductor.
Keep the switch node (SW) away from the feedback
To minimize noise, place a ground plane underneath
Use a wide trace to connect the output capacitor
ground terminal to the input capacitor ground
Phase margin will change as the output capacitor
value and ESR changes. Contact the factory if the
output capacitor is different from what is shown in
The feedback trace should be separate from the
power trace and connected as close as possible to
the output capacitor. Sensing a long high current
load trace can degrade the DC load regulation.
If 0603 package ceramic output capacitors are used,
then make sure that it has enough capacitance at
the desired output voltage. Please refer to the
capacitor datasheet for more details.
The external Schottky diode is placed next to the
The connection from the Schottky diode’s Anode to
the input capacitors ground terminal must be as
short as possible.
The diode’s Cathode connection to the switch node
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