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MIC24420 Datasheet(PDF) 21 Page  Micrel Semiconductor 

MIC24420 Datasheet(HTML) 21 Page  Micrel Semiconductor 
21 / 34 page Micrel, Inc. MIC24420/MIC24421 June 2012 21 M9999062012C The modulator, filter and voltage divider gains can be multiplied together to show the open loop gain of these parts. Gmod H Gfilter(s) Gvd(s) ⋅ ⋅ = This transfer function is plotted in Figure 13. At low frequency, the transfer function gain equals the modulator gain times the voltage divider gain. As the frequency increases toward the LC filter resonant frequency, the gain starts to peak. The increase in the gain’s amplitude equals Q. Just above the resonant frequency, the gain drops at a 40db/decade rate. The phase quickly drops from 0° to almost 180° before the phase boost of the zero brings it back up to 90°. Higher values of Q will cause the phase to drop quickly. In a well damped, low Q system the phase will change more slowly. As the Gain/Phase plot approaches the zero frequency (fZ), formed by CO and its ESR, the slope of the gain curve changes from 40db/dec. to 20db/dec and the phase increases. The zero causes a 90° phase boost. Ceramic capacitors, with their smaller values of capacitance and ESR, push the zero and its phase boost out to higher frequencies, which allow the phase lag from the LC filter to drop closer to 180°. The system will be close to being unstable if the overall open loop gain crosses 0dB while the phase is close to 180°. Figure 13: Gvd Transfer Function If the output capacitance and/or ESR is high, the zero moves lower in frequency and helps to boost the phase, leading to a more stable system. Error Amplifier Poles and Zeros The error amplifier has internal poles and zeros that can be shifted in frequency with an external capacitor. The general form of the error amplifier compensation is shown in the equation below: ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ + ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ + ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ + ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ + × = ωp2 s 1 ωp1 s 1 ωz2 s 1 ωz1 s 1 G Gea(s) DC The GDC is the DC gain of the error amplifier. It is internally set to 2500 (68dB). As illustrated in Figure 12, there are two compensating zeros. ωz1 is internally set with R3 and C3. The zero frequency is fixed at a nominal 16kHz in the MIC24420/MIC24421. The second zero, ωz2, is set by the external capacitor, C2. For the MIC24420: C2 10 21 π 2 1 fz2 16kHz C3 R3 π 2 1 fz1 100pf C3 100k R3 3 × ⋅ × × = = × × × = = = The two compensating pole frequencies are shown below. C2 10 12 π 2 1 fp2 250Hz fp1 3 × ⋅ × × = = Gv d Transfer Function 50 40 30 20 10 0 10 20 30 40 50 10 100 1000 10000 100000 1000000 FREQ UENCY (Hz) 210 180 150 120 90 60 30 0 30 60 90 Gain Phase VIN = 12V VOUT = 1.8V COUT = 20µF L = 4.7µH fp2 and fz2 both depend on the value of C2 and are proportionally spaced in frequency with the zero at a lower frequency than the pole. This provides gain and phase boost in the control loop. Voltage Divider Feedforward Capacitor The capacitor across the upper voltage divider resistor boosts the gain and phase of the control loop by short circuiting the highside resistor at higher frequencies. The capacitor and upper resistor form a zero at a lower frequency. The capacitor and parallel combination of upper and lower resistors form a pole at a higher frequency. This phase boost circuit is most effective at higher output voltages, where there is a larger attenuation from the voltage divider resistors. 
