Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF HTML

MIC24420 Datasheet(PDF) 12 Page - Micrel Semiconductor

Part No. MIC24420
Description  2.5A Dual Output PWM Synchronous Buck Regulator IC
Download  34 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  MICREL [Micrel Semiconductor]
Homepage  http://www.micrel.com
Logo 

MIC24420 Datasheet(HTML) 12 Page - Micrel Semiconductor

Zoom Inzoom in Zoom Outzoom out
 12 / 34 page
background image
Micrel, Inc.
MIC24420/MIC24421
June 2012
12
M9999-062012-C
Soft-start
Enable and soft-start waveforms are shown in Figure 2.
Figure 2. Soft-start Timing Diagram
A capacitor, CSS, is connected to the EN/DLY pin. The
CSS capacitor range is 4.7nF to 22nF. Releasing the pin
allows an internal current source to charge the capacitor.
The delay (tD) between the EN/DLY pin release and
when VOUT starts to rise can be calculated by the
equation below.
SS
Start
Threshold_
SS
D
I
V
C
t
×
=
Where:
CSS is the soft-start capacitor.
ISS is the internal soft-start current (7µA nominal).
VThreshold_start is the EN/DLY pin voltage where the output
starts to rise (1.35V nominal).
The output voltage starts to rise when voltage on the
EN/DLY pin reaches the start threshold. The output
voltage reaches regulation when the EN/DLY pin voltage
reaches the end threshold. The output voltage rise time
(tR) can be calculated by the equation below:
SS
Start
Threshold_
End
Threshold_
SS
R
I
)
V
(V
C
t
×
=
Where:
VThreshold_End is the EN/DLY pin voltage where the output
reaches regulation (2.4V nominal).
As the MIC24420/MIC24421 uses a fold-back, hiccup
mode current limit, care should be taken to select tR to
ensure startup. See application information for details.
Power Good
Power good is an open drain signal that asserts when
VOUT exceed the power good threshold. The circuit
monitors the FB pin. The internal FET is turned on while
the FB voltage is below the FB threshold. When voltage
on the FB in exceeds the FB threshold, the FET is
turned off. A pull-up resistor can be connected to PVDD
or an external source. The external source voltage must
not exceed the maximum rating of the pin. The PG pin
can be connected to another regulator’s EN/DLY pin for
sequencing of the outputs. A pull-up resistor is not used
when the power good pin is connected to another
regulators EN/DLY pin.
Output Sequencing
Sequencing of the outputs can be easily implemented as
shown in Figure 3. The power good pin is used to
disable VOUT2 until the VOUT1 reaches regulation.
Sequencing waveforms are shown in Figure 4.
Figure 3. Output Sequencing
Figure 4. Output Sequencing Waveforms


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn