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ISL62773HRZ Datasheet(PDF) 16 Page - Intersil Corporation |
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ISL62773HRZ Datasheet(HTML) 16 Page - Intersil Corporation |
16 / 37 page ISL62773 16 March 7, 2012 FN8263.0 Start-up Timing With VDD above the POR threshold, the controller start-up sequence begins when ENABLE exceeds the logic high threshold. Figure 13 shows the typical soft-start timing of the Core and Northbridge VRs. Once the controller registers ENABLE as a high, the controller checks that state of a few programming pins during the typical 8ms delay prior to beginning soft-starting the Core and Northbridge outputs. The pre-PWROK Metal VID is read from the state of the SVC and SVD pins and programs the DAC, the programming resistors on COMP, COMP_NB, and FCCM_NB are read to configure internal drivers, switching frequency, slew rate, output offsets. These programming resistors are discussed in subsequent sections. The ISL62773 uses a digital soft-start to ramp up the DAC to the Metal VID level programmed. The soft-start slew rate is programmed by the FCCM_NB resistor which is used to set the VID-on-the-Fly slew rate as well. See “VID- on-the-Fly Slew Rate Selection” on page 21 for more details on selecting the FCCM_NB resistor. PGOOD is asserted high at the end of the soft-start ramp. Voltage Regulation and Load Line Implementation After the soft-start sequence, the ISL62773 regulates the output voltages to the pre-PWROK metal VID programmed, see Table 6. The ISL62773 controls the no-load output voltage to an accuracy of ±0.5% over the range of 0.75V to 1.55V. A differential amplifier allows voltage sensing for precise voltage regulation at the microprocessor die. VDD SVC SVD ENABLE PWROK VCORE/ VCORE_NB 1 7 8 FIGURE 12. SVI INTERFACE TIMING DIAGRAM: TYPICAL PRE-PWROK METAL VID START-UP PGOOD & PGOOD_NB 3 4 2 5 6 METAL_VID V_SVI Interval 1 to 2: ISL62773 waits to POR. Interval 2 to 3: SVC and SVD are externally set to pre-Metal VID code. Interval 3 to 4: ENABLE locks pre-Metal VID code. Both outputs soft-start to this level. Interval 4 to 5: PGOOD signal goes HIGH, indicating proper operation. Interval 6 to 7: SVC and SVD data lines communicate change in VID code. Interval 7 to 8: ISL62773 responds to VID-ON-THE-FLY code change and issues a VOTF for positive VID changes. Interval 5 to 6: PGOOD and PGOOD_NB high is detected and PWROK is taken high. The ISL62773 is prepared for SVI commands. SVT Telemetry Telemetry VOTF Post 8: Telemetry is clocked out of the ISL62773. VDD ENABLE DAC 8ms MetalVID SLEW RATE VID COMMAND VOLTAGE PGOOD PWROK VIN FIGURE 13. TYPICAL SOFT-START WAVEFORMS |
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