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PCA9555N Datasheet(PDF) 3 Page - NXP Semiconductors |
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PCA9555N Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 34 page PCA9555_8 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 08 — 22 October 2009 3 of 34 NXP Semiconductors PCA9555 16-bit I2C-bus and SMBus I/O port with interrupt 4. Block diagram 5. Pinning information 5.1 Pinning Remark: All I/Os are set to inputs at reset. Fig 1. Block diagram of PCA9555 PCA9555 POWER-ON RESET 002aac702 I2C-BUS/SMBus CONTROL INPUT FILTER SCL SDA VDD INPUT/ OUTPUT PORTS IO0_0 VSS 8-bit write pulse read pulse IO0_2 IO0_1 IO0_3 IO0_4 IO0_5 IO0_6 IO0_7 INPUT/ OUTPUT PORTS IO1_0 8-bit write pulse read pulse IO1_2 IO1_1 IO1_3 IO1_4 IO1_5 IO1_6 IO1_7 INT A1 A0 A2 LP filter VDD Fig 2. Pin configuration for DIP24 Fig 3. Pin configuration for SO24 VDD SDA SCL A0 IO1_7 IO1_6 IO1_5 IO1_4 IO1_3 IO1_2 IO1_1 IO1_0 INT A1 A2 IO0_0 IO0_1 IO0_2 IO0_3 IO0_4 IO0_5 IO0_6 IO0_7 VSS PCA9555N 002aac697 1 2 3 4 5 6 7 8 9 10 11 12 14 13 16 15 18 17 20 19 22 21 24 23 INT VDD A1 SDA A2 SCL IO0_0 A0 IO0_1 IO1_7 IO0_2 IO1_6 IO0_3 IO1_5 IO0_4 IO1_4 IO0_5 IO1_3 IO0_6 IO1_2 IO0_7 IO1_1 VSS IO1_0 PCA9555D 002aac698 1 2 3 4 5 6 7 8 9 10 11 12 14 13 16 15 18 17 20 19 22 21 24 23 |
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